Instruction prefetch mechanism utilizing a branch predict instru

Details Instruction prefetch mechanism utilizing a branch predict instru Instruction prefetch mechanism utilizing a branch predict instru

1996-07-24

1998-04-21

Treat, William M.

395383, G06F 938

Patent

active

057428042

ABSTRACT:
A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

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Sites et al., Alpha Architecture Reference Manual, Digital Equipment Corporation, pp. (I) 4-115,4-116, A-10,A-11, Jul. 1992.

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