Instruction prefetch circuit and cache device with branch detect

Details Instruction prefetch circuit and cache device with branch detect Instruction prefetch circuit and cache device with branch detect

1995-10-05

1998-03-17

Lim, Krisna

395581, 395582, G06F 938

Patent

active

057297070

ABSTRACT:
In an instruction prefetch circuit, even when a branch instruction is prefetched, the circuit continues a prefetch operation until branching is actually executed. Accordingly, when the branch instruction is a conditional branch instruction and not actually executed, the circuit continues the prefetch operation so that the prefetched instructions are efficiently supplied to a processor. It may be arranged that, when the branch instruction is an unconditional branch instruction, a branch destination address is extracted from the unconditional branch instruction and used as a prefetch address. Accordingly, the circuit continues the prefetch operation even when branching is executed. It may further be arranged that, when the branch instruction is a conditional branch instruction, a branch destination address is extracted from the conditional branch instruction and further a branch prediction is performed. When branching is expected based on the branch prediction, the branch destination address is used as a prefetch address. Accordingly, as long as the branch prediction does not fail, the circuit continues the prefetch operation.

REFERENCES:
patent: 4847753 (1989-07-01), Matsuo et al.
patent: 4881170 (1989-11-01), Morisada
patent: 4984154 (1991-01-01), Hanatani et al.
patent: 5283873 (1994-02-01), Steely, Jr. et al.
patent: 5327536 (1994-07-01), Suzuki
patent: 5507028 (1996-04-01), Liu
patent: 5542109 (1996-07-01), Blomgren et al.
patent: 5586278 (1996-12-01), Papworth et al.
Scott McFarling and John Hennessy, Reducing the Cost of Branches, 1986, IEEE pp. 396-403.
Johnny K. F. Lee and Alan Jay Smith, Branch Prediction Strategies and Branch Target Buffer Design, Jan. 1984, pp. 6-22.
IBM Technical Disclosure Bulletin, Efficient Scheme to Reduce Over-Prefetching of Instructions for Loading an Instruction Buffer, 1990, pp. 423-425.

Affiliated with

Also associated with

Rating

Instruction prefetch circuit and cache device with branch detect does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Instruction prefetch circuit and cache device with branch detect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction prefetch circuit and cache device with branch detect will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-966373