Instruction predecode and multiple instruction decode

Details Instruction predecode and multiple instruction decode Instruction predecode and multiple instruction decode

1996-05-16

1998-09-15

Treat, William M.

395388, 395389, 39580023, G06F 922

Patent

active

058092730

ABSTRACT:
Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by predecoding each byte of an instruction, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoding operation associates an instruction length to each instruction byte. The instruction length is found for some instructions by reading a single instruction byte. For other instructions require more information to determine the instruction length and two or three instruction bytes are read. Based on the instruction length determination, instructions are classified into a group of instructions in which multiple instructions are decoded in parallel and a group of instructions in which multiple instructions are not decoded in parallel. Predecode information including a designation of instruction length and a designation of classification group is stored for each instruction byte. The instruction bytes and associated predecode information are applied to a decoder that includes a plurality of first group instruction decoders for decoding a plurality of parallel-decodable instructions in parallel and a second group instruction decoder for decoding instructions that are not decodable in parallel.

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