Instruction nullification system and method for a processor that

Details Instruction nullification system and method for a processor that Instruction nullification system and method for a processor that

1996-05-15

1998-08-25

Harrell, Robert B.

395392, 395376, 395586, 395580, 395800, G06F 932

Patent

active

057991677

ABSTRACT:
An instruction nullification system facilitates handling of nullification dependencies in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order. After execution, instructions are retired by a retire mechanism, which transforms the results of instruction execution to the architecture state. Predictions are made as to whether instructions are dependent upon nullify instructions, such as a branch instruction. A dependent instruction can potentially be nullified by the nullify instruction. A dependent instruction is permitted to execute when it is predicted as not potentially nullified, regardless of when its corresponding nullify instruction commences execution. A dependent instruction is prevented from executing when they are predicted as potentially nullified, until its corresponding nullify instruction commences execution and until the nullify instruction writes the result to the target register corresponding with the dependent instruction. When the dependent instruction is mispredicted as not potentially nullified, then it is invalidated and re-executed. When the dependent instruction is mispredicted as potentially nullified, then it is validated, and its result is utilized.

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