Instruction methods for performing data formatting while moving

Details Instruction methods for performing data formatting while moving Instruction methods for performing data formatting while moving

1996-09-20

1998-09-22

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

345513, G06F 1300

Patent

active

058121471

ABSTRACT:
Instruction methods for moving data between memory and a vector register file while performing data formatting. The methods are processed by a processor having a vector register file and a memory unit. The methods are useful in the graphics art because they allow more efficient movement and processing of raster formatted graphics data. The vector register file has a number of vector registers (e.g., 32) that each contain multi-bits of storage (e.g., 128 bits). In one class of instructions, eight byte locations within memory are simultaneously loaded into eight separate 16 bit locations within a register of the register file. The data can be integer or fraction and signed or unsigned. The data can also be stored from the register file back to memory. In a second class of instructions, alternate locations of a memory qaudword are selected and simultaneously loaded in the register file. In a third class, data is obtained across a word boundary by a first instruction that obtains a first part and a second instruction that obtains the remainder part crossing the boundary. In a last class of instruction transfers, a block (e.g., 8 16-bit.times.8 16-bit) of data is loaded from memory, stored in the register file and stored back into memory causing a transposition of the data block (16 cycles). A block (e.g., 8 16-bit.times.8 16-bit) of data is stored from the register file to memory, and loaded back into the register file causing a transposition of the data block (16 cycles).

REFERENCES:
Microprocessor Report, "UltraSpare Adds Multimedia Instruction" by Linley Gwennap, Dec. 5, 1994.
Motorola, MC88110--Second Generation RISC Microprocessor User's Manual; Sections 1 and 5; pp. 10-47 to 10-49, 10-76 to 10-78, 10-90 and 10-91, 1991.

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