Instruction group formation and mechanism for SMT dispatch

Details Instruction group formation and mechanism for SMT dispatch Instruction group formation and mechanism for SMT dispatch

2007-06-26

2007-06-26

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction decoding

Predecoding of instruction component

C712S215000, C712S216000

Reexamination Certificate

active

10965143

ABSTRACT:
A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads. When the resource availability equals or exceeds the resource requirements for a group of instructions, those instructions can be dispatched simultaneously to the hardware resources. A start bit may be inserted in one of the program instructions to define the instruction group. The hardware resources may in particular be execution units such as a fixed-point unit, a load/store unit, a floating-point unit, or a branch processing unit.

REFERENCES:
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5828895 (1998-10-01), Chan et al.
patent: 5958042 (1999-09-01), Tremblay

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