Instruction generator architecture for a video signal processor

Details Instruction generator architecture for a video signal processor Instruction generator architecture for a video signal processor

1989-10-13

1993-05-11

Fleming, Michael R.

Boots, shoes, and leggings

364DIG1, 364228, 3642283, 3642306, 3642372, 3642378, 364247, 3642476, 364262, 3642624, G06F 1300

Patent

active

052108368

ABSTRACT:
A synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided.

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