Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
2007-06-26
2007-06-26
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
Reexamination Certificate
active
09595776
ABSTRACT:
In a multi-streaming processor having a memory cache, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and a hit/miss predictor for forecasting whether a load instruction will hit or miss the cache. The prediction by the hit-miss predictor is used by the fetch algorithm in determining from which stream to fetch. A hit prediction results in a next instruction being fetched from the same stream as the instruction tested by the hit/miss predictor, while a miss prediction results in the next instruction being fetched from a different stream, if any. The predictor is also used to determine which instructions to dispatch to functional units.
REFERENCES:
patent: 4197579 (1980-04-01), Forsman et al.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 5142676 (1992-08-01), Fried et al.
patent: 5309173 (1994-05-01), Izzi et al.
patent: 5321823 (1994-06-01), Grundmann et al.
patent: 5361337 (1994-11-01), Okin
patent: 5461722 (1995-10-01), Goto
patent: 5511210 (1996-04-01), Nishikawa et al.
patent: 5535365 (1996-07-01), Barriuso et al.
patent: 5542088 (1996-07-01), Jennings, Jr. et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5572704 (1996-11-01), Bratt et al.
patent: 5600837 (1997-02-01), Artieri
patent: 5604877 (1997-02-01), Hoyt et al.
patent: 5632025 (1997-05-01), Bratt et al.
patent: 5649144 (1997-07-01), Gostin et al.
patent: 5694572 (1997-12-01), Ryan
patent: 5701432 (1997-12-01), Wong et al.
patent: 5713038 (1998-01-01), Motomura
patent: 5745778 (1998-04-01), Alfieri
patent: 5748468 (1998-05-01), Notenboom et al.
patent: 5758142 (1998-05-01), McFarling et al.
patent: 5784613 (1998-07-01), Tamirsa
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5815733 (1998-09-01), Anderson et al.
patent: 5852726 (1998-12-01), Lin et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5867725 (1999-02-01), Fung et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5913054 (1999-06-01), Mallick et al.
patent: 5933627 (1999-08-01), Parady
patent: 5946711 (1999-08-01), Donnelly
patent: 5987492 (1999-11-01), Yue
patent: 6016542 (2000-01-01), Gottlieb et al.
patent: 6018759 (2000-01-01), Doing et al.
patent: 6029228 (2000-02-01), Cai et al.
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6061710 (2000-05-01), Eickemeyer et al.
patent: 6076157 (2000-06-01), Borkenhagen et al.
patent: 6105127 (2000-08-01), Kozo et al.
patent: 6115802 (2000-09-01), Tock et al.
patent: 6119203 (2000-09-01), Snyder et al.
patent: 6192384 (2001-02-01), Dally et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6260077 (2001-07-01), Rangarajan et al.
patent: 6308261 (2001-10-01), Morris et al.
patent: 6356996 (2002-03-01), Adams
patent: 6430593 (2002-08-01), Lindsley
patent: 6442675 (2002-08-01), Derrick et al.
patent: 6487571 (2002-11-01), Voldman
patent: 6493749 (2002-12-01), Paxhia et al.
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 6789100 (2004-09-01), Nemirovsky et al.
patent: 2003/0084269 (2003-05-01), Drysdale et al.
patent: 2005/0081214 (2005-04-01), Nemirovsky et al.
patent: 0806730 (1997-11-01), None
patent: 0827071 (1998-03-01), None
patent: 0953903 (1999-11-01), None
patent: 2103630 (1988-10-01), None
patent: 63254530 (1988-10-01), None
patent: 4335431 (1992-11-01), None
patent: 546379 (1993-02-01), None
patent: 09506752 (1997-06-01), None
patent: 1011301 (1998-01-01), None
patent: 10124316 (1998-05-01), None
patent: 10207717 (1998-08-01), None
patent: WO9427216 (1994-11-01), None
patent: WO0023891 (2000-04-01), None
Yoaz et al., Speculation Techniques for Improving Laod Related Instruction Scheduling, 1999, pp. 42-53.
Kessler, R.E., The Alpha 21264 Microprocessor: Out-of-Order Execution at 600 Mhz, Aug. 1998, pp. 18-19.
McFarling, “WRL Technical Note TN-36: Combining Branch Predictors,” 1993, p. 11-12.
Fiske et al., “Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors”, 1995, pp. 210-221, IEEE.
Steere et al., “A Feedback—Driven Proportion Allocator for Real-Rate Scheduling”, Third Symposium on Operating Systems Design and Implementation, Feb. 1999, pp. 145-158, USENIX Association.
Tullsen et al., “Slmultaneous Multlthreading: Maximizing on-Chip Parallelism”, 22nd Annual International Symposium on Computer Architecture, Jun. 1995, Santa Margherita Ligure, Italy.
Donalson et al., “DISC: Dynamic Instruction Stream Computer, An Evaluation of Performance”, 26th Hawaii Confernce on Systems Sciences, 1993, pp. 448-456, vol. 1.
Nemirovsky et al., DISC: Dynamlc Instruction Stream Computer, ACM, 1991, pp. 163-171.
Tullsen, Dean et al., Supporting Flne-Grained Synchronization on a Simultaneous Multithreading Processor, UCSD CSE Technical Report CS98-587, Jun. 1998, all pages, US.
Nemirovsky et al., “Quantitative Study of Data Caches on a Multistreamed Architecture”, Workshop on Mutlithreaded Execution Archltecture and Compilation, Jan. 1998.
Li et al., “Design and Implementation of a Multlple-Instructlon-Stream Multlple-Execution-Pipeline Archltecture”, 7th Internatlonal Conference on Parallel amd Distributed Computing and Systems. Oct. 1995. Washington D.C.
Yamamoto et al., Performance Estlmation of Multistreamed, Superscalar Processors, IEEE. 1994, pp. 195-204, Hawaii, US.
Yamamoto, Wayne.An Analysis of Multistreamed, Superscalar Processor Architectures.University of California Santa Barbara Dissertation. Dec. 1995. Santa Barbara, US.
Yamamoto et al. “Increasing Superscalar Performance Through Multistreaming.”Parallel Architectures and Compilation Techniques(PACT '95). 1995.
The PowerPC Architecture:A Specification for a New Family of RISC Processors. 2ndEd. May 1994. pp. 70-72. Morgan Kaufmann. San Francisco, US.
MC68020 32-Bit Microprocessor User's Manual. 3rdEd.. 1989. pp. 3-125, 3-126, and 3-127. Prentice Hall, NJ, US.
Potel, M.J. “Real-Time Playback in Animation Systems.”Proceedings of the 4thAnnual Conference on Computer Graphics and Interactive Techniques.1997. pp. 72-77, San Jose, CA, US.
ARM Architecture Reference Manual.1996. pp. 3-41, 3-42, 3-43, 3-67, and 3-68. Prentice Hall, NJ, US.
ESA/390 Principles of Operation.IBM Online Publications Center Reference No. SA22-7201-08. Table of Contents and paras. 7.5.31 and 7.5.70. IBM Corporation. Boulder, CO, US.
MC88110 Second Generation RISC Microprocessor User's Manual. 1991. pp. 10-66, 10-67, and 10-71. Motorola, Inc.
Diefendorff, Keith et al. “Organization of the Motorola 88110 Superscalar RISC Microprocessor.”IEEE Journal of Microelectronics. Apr. 1992. pp. 40-63. vol. 12, No. 2. IEEE. New York, NY, US.
Kane, Gerry.PA-RISC 2.0 Architecture. 1996, pp. 7-106 and 7-107. Prentice Hall. NJ, US.
Difendorff, Keith et al. “AltiVec Extension to PowerPC Accelerates Media Processing.”IEEE Journal of Microelectronics.vol. 20, No. 2 (2000): pp. 85-95.
Grunewald, Winfried et al. “Towards Extremely Fast Context Switching in a Block Multithreaded Processor.”Proceedings of EUROMICRO 22, 1996. pp. 592-599.
Bradford, Jeffrey et al. “Efficient Synchronization for Multithreaded Processors.”Workshop on Multithreaded Execution, Architecture, and Compilation.Jan.-Feb. 1998. pp. 1-4.
Pai, Vijay et al. “An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors.”Proceedings of ASPLOS-VII, Oct. 1996: pp. 12-23, ACM, Inc.
Yoaz et al. “Speculation Techniques for Improving Load Related Instruction Scheduling.” 1999. pp. 42-53, IEEE.
Kessler, R. E. “The Alpha 2164 Microprocessor: Out-of-Order Execution at 600 MHz.” Aug. 1998.
Donaldson et al. “DISC: Dynamic Instruction Stram Computer, An Evaluation of Performance.”26thHawaii Conference on Systems Sciences.vol. 1. 1993. pp. 448-456.
Nemirovsky et al. “DISC: Dynamic Instruction Str
Musoll Enric
Nemirovsky Mario
Boys Donald R.
Chan Eddie
Huffman James W.
Huffman Richard K.
Huisman David J.
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