Instruction fetch bandwidth analysis

Details Instruction fetch bandwidth analysis Instruction fetch bandwidth analysis

1996-12-17

1999-03-09

Lall, Parshotam S.

39518401, 39518306, 395382, 395394, G06F 1500, G06F 1134

Patent

active

058813063

ABSTRACT:
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

REFERENCES:
patent: 5546599 (1996-08-01), Song
patent: 5548738 (1996-08-01), Song
patent: 5559976 (1996-09-01), Song
patent: 5651125 (1997-07-01), Witt et al.
patent: 5691920 (1997-11-01), Levine et al.
patent: 5729726 (1998-03-01), Levine et al.
Serial No. 08/497,242, entitled "Method and System for Halting Processor Execution in Response to an Enumerated Occurrence of a Selected Combination of Internal States".
Serial No. 08/485,953, entitled, "On-Chip Performance Monitoring with a Characterization of Locks/Semaphore Utilization".
Serial No. 08/537,586, entitled "A Method and System for Performance Monitoring Through Indentification of Frequency and Length of Time of Execution of Serialization Instructions in a Processing System".
Serial No. 08/537,645, entitled "A Method and System for Performance Monitoring Through Monitoring an Order of Processor Events During Execution in a Processing System".
Serial No. 08/538,102, entitled "A Method and System for Performance Monitoring Stalls to Identify Pipeline Bottlenecks and Stalls in a Processing System".
Serial No. 08/538,509, entitled "A Method and System for Performance Montoring Efficiency of Branch Unit Operation in a Processing System".
Serial No. 08/538,774, entitled "A Method and System for Performance Monitoring of Dispatch Stalls in a Processing System".
Serial No. 08/538,070, entitled "A Method and System Performance Montoring of Disptach Unit Efficiency in a Processing System".
Serial No. 08/734,335, entitled "Performance Monitor".
Serial No. 08/766,143, entitled "CPI Infinite and Finite Analysis".
Serial No. 08/767,656, entitled "Instruction Parallelism Analysis".
Serial No. 08/767,655, entitled "Load Stall Analysis".
Serial No. 08/767,662, entitled "Trailing Edge Analysis".
Serial No. 08/767,706, entitled "Operand Fetch Bandwidth Analysis".
Serial No. 08/536,492, entitled "A Mehof ans System for Performance Monitoring of Misaligned Memory Accesses in a Processing System".
Serial No. 08/538,071, entitled "A Method and System for Selecting and Distinguishing an Event Sequence Using an Effective Address in a Processing System".
Serial No. 08/539,023, entitled "A Method and System for Performance Monitoring Time Lengths of Disabled Interrupts in a Processing System".
IBM (PowerPC 604 RISC Microprocessor User's Manual ), Chapter p, pg. 9-4 and 9-5, 1994.
IBM (Addendum to PowerPC 604 RISC Microprocessor Supplement and User's Manual Errata), pg. 18-20 and pg. 35-37, 1996.

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