Instruction execution mechanism

Details Instruction execution mechanism Instruction execution mechanism

2000-03-10

2003-05-13

Morse, Gregory (Department: 2122)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S127000, C717S159000, C712S227000

Reexamination Certificate

active

06564373

ABSTRACT:

BACKGROUND TO THE INVENTION
This invention relates to a mechanism for executing instructions in a computer system.
The invention is particularly concerned with a computer system in which source code instructions are translated into target code instructions for execution on a particular processor. This may be required, for example, where one processor is being used to emulate another, in which case the instructions for the processor being emulated must be translated into instructions for the emulating processor.
One approach, referred to as interpretation, is to create a software model of the instruction set of the processor being emulated. This model operates by reading each target instruction, decoding it, and selecting one of a number of sequences that perform the same function as the instruction being emulated. This fetch/decode/execute sequence is repeated for each source code instruction in turn.
A more efficient approach is to translate a block of source code instructions, rather than a single instruction. That is, the source code is divided into blocks, and each source code block is translated into a block of target code instructions, functionally equivalent to the source code block. Typically, a block has a single entry point and one or more exit points. The entry point is the target of a source code jump, while the (or each) exit is a source code jump.
Translating blocks is potentially much more efficient, since it provides opportunities for eliminating redundant instructions within the target code block, and other optimisations. Known optimising compiler techniques may be employed for this purpose. To increase efficiency further, the target code blocks may be held in main memory and/or a cache store, so that they are available for re-use if the same section of code is executed again, without the need to translate the block.
The present invention is concerned with the problem of sequencing the execution of such blocks, to ensure that each block is followed by an appropriate successor block. The object of the present invention is to provide an improved method for sequencing execution of code blocks.
SUMMARY OF THE INVENTION
According to the invention, a method of executing instructions in a computer system, comprises:
(a) storing a plurality of blocks of instructions, each block having a specified set of entry conditions associated with it;
(b) on completion of execution of a current block of instructions, searching for potential successor blocks; and
(c) for each potential successor block, comparing the set of entry conditions associated with that block with the exit conditions of the current block of instructions and, if a match is found, selecting the potential successor block as the current block and executing it.
It will be seen that the invention permits the use of multiple blocks for different entry conditions. The use of such multiple blocks is advantageous, in that each block can be tailored to its specific entry conditions, thereby improving its efficiency of execution. A preferred form of the invention also allows block-following code to be planted in the blocks, to optimise the sequencing between the blocks.
One embodiment of the invention will now be described by way of example with reference to the accompanying drawings.


REFERENCES:
patent: 5428786 (1995-06-01), Sites
patent: 5507030 (1996-04-01), Sites
patent: 5590329 (1996-12-01), Goodnow et al.
patent: 5613118 (1997-03-01), Heisch et al.
patent: 5721927 (1998-02-01), Baraz
patent: 5751982 (1998-05-01), Morley
patent: 5894576 (1999-04-01), Bharadwaj
patent: 5950009 (1999-09-01), Bortnikov et al.
patent: 6044220 (2000-03-01), Breternitz, Jr.
patent: 6192513 (2001-02-01), Subrahmanyam
patent: 0 927 929 (1999-07-01), None
patent: 0 930 572 (1999-07-01), None
patent: WO 92/15937 (1992-09-01), None

Affiliated with

Also associated with

Rating

Instruction execution mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Instruction execution mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction execution mechanism will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3085575