Instruction execution mechanism

Details Instruction execution mechanism Instruction execution mechanism

1999-10-15

2003-03-11

Coleman, Eric (Department: 2783)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C717S159000

Reexamination Certificate

active

06532532

ABSTRACT:

BACKGROUND TO THE INVENTION
This invention relates to an instruction execution mechanism for a computer system.
The invention is particularly concerned with a computer system in which source instructions are translated into target instructions for execution on a particular processor. This may be required, for example, where one processor is being used to emulate another, in which case the instructions for the processor being emulated must be translated into instructions for the emulating processor.
One approach, referred to as interpretation, is to translate the instructions one at a time. That is, each source instruction is translated into a sequence of one or more target instructions, without reference to any other source instructions. Interpretation can be very inefficient, since each source instruction may be translated into a long sequence of target instructions, resulting in very poor performance.
A more efficient approach is to use a block of source instructions as the unit of translation, rather than a single instruction. That is, the source code is divided into blocks, and each source code block is translated into a block of target instructions, functionally equivalent to the source code block. Typically, a block has a single entry point and one or more exit points. The entry point is the target of a source code jump, while the (or each) exit is a source code jump.
Using blocks as the units of translation is potentially much more efficient, since it provides opportunities for eliminating redundant instructions within the target code block, and other optimisations. Known optimising compiler techniques may be employed for this purpose.
The target code blocks may be held main memory and/or a cache store, so that they are available for re-use if the same section of code is executed again, without the need to translate the block. The blocks held in main memory clearly need to be managed, because memory is a finite resource and their usage changes over time, reflecting changes in behaviour of the system. In particular, source code blocks may be deleted, changed, or simply paged out to make room for other blocks.
It has been shown that the size of the source code blocks heavily influences the effectiveness of the translation. Larger source code blocks tend to give better performance by reducing inter-block overheads and by allowing greater scope for optimisation within both the source code and target code blocks. Also, larger target code blocks tend to be easier to manage, since there are fewer of them.
On the other hand, if very large source code blocks are used, large amounts of code may be translated and stored unnecessarily. This results in an increased translation overhead, and wastes storage space.
The object of the present invention is to provide a way of benefiting from the advantages of larger-sized blocks, while avoiding the disadvantages.
SUMMARY OF THE INVENTION
According to the invention, a computer system comprises:
(a) translation means for translating blocks of instructions from a source code into a target code;
(b) execution means for executing the blocks, while building up dynamic behaviour information about relationships between the blocks; and
(c) block coalition means for selecting a related group of blocks on the basis of the dynamic behaviour information, and combining the selected group of blocks to form a new block of target code instructions that is functionally equivalent to the combination of the selected group of blocks.
It can be seen that the invention allows the system to start with relatively small blocks, and then to combine them into larger blocks, based on the dynamic behaviour of the code. This provides a way of maximising performance without wasting too much store space.
One computer system embodying the invention will now be described by way of example with reference to the accompanying drawings.


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