Instruction decoder for a variable byte processor

Details Instruction decoder for a variable byte processor Instruction decoder for a variable byte processor

1988-01-06

1990-09-18

Shaw, Gareth D.

Boots, shoes, and leggings

364262, 3642624, 3642449, 364244, 3642513, 364251, G06F 932

Patent

active

049582755

ABSTRACT:
An instruction decoder, for a variable byte processor, is capable of making the variable byte processor operate at a high processing speed and high byte efficiency. The instruction decoder includes an instruction register which stores instructions applied to an internal data bus, a first instruction decoding unit which provides a consecutive instruction execution mode signal specifying the repetitive execution of the instruction read from the instruction register for different operands stored at different addresses, a consecutive instruction execution cycle monitoring unit which counts the number of execution cycles of the instruction and provides a signal indicating the completion of the repetitive execution of the instruction, register/counters which count the number of execution cycles and provide operands of different addresses every time an execution cycle is completed, a second instruction decoding unit which sequentially specifies data stored at different operand addresses in response to the output signals of the register/counters, and a gate which inhibits the instruction register from reading a new instruction until the instruction is repeated by the specified number of execution cycles.

REFERENCES:
patent: 3466613 (1969-09-01), Schlaeppi
patent: 3665411 (1972-05-01), O'Connor
patent: 3771141 (1973-11-01), Culler
patent: 4037213 (1977-07-01), Atkins et al.
patent: 4118776 (1978-10-01), Isomura
patent: 4202035 (1980-05-01), Lane
patent: 4306287 (1981-12-01), Huang
"A 2-.mu.m CMOS 8-MIPS Digital Signal Processor with Parallel Processing Capability"; IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct., 1986; pp. 750-765.

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