1996-11-26
1999-08-10
Trammell, James P.
395707, 395708, G06F 944
Patent
active
059371889
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a device for creating a sequence of instructions for operating the same, or a different, target device.
BACKGROUND ART
It is known to provide devices for translating a sequence of instructions in a high level computer language (such as FORTRAN) into a sequence of machine level instructions for subsequent execution. Such a device comprises a programmable computer operating under control of a programme (termed a "compiler") which operates in accordance with a fixed series of rules, and may produce code which is repetitive and uses a large volume of memory, or operates slowly.
Furthermore, the high level language imposes an algorithmic structure specifying an order in which operations are to performed by the target device, which may in fact be wasteful of the memory and other resources of the device.
SUMMARY OF THE INVENTION
The technical problem addressed by the present invention is to provide a device which creates a sequence of instructions for subsequent execution which is efficient (for example in execution speed or in number of instructions and hence required memory).
Accordingly, in one aspect, the invention provides a device for creating instructions arranged to generate multiple alternative sequences of instructions performing the same function, and to select one of said sequences.
In one aspect, the device may comprise input means for accepting a function to be executed by the instructions in the form of one or more logical relationships. Alternatively, in another aspect, the device may comprise input means which can accept input from a user in the form of a human language, and convert the input to one or more logical relationships.
In these aspects, the device can accept an input which specifies the result to be achieved by the instruction sequence, and not the algorithm for achieving the result. This enables the device to produce a sequence of instructions which is optimal without being constrained by the particular order in which the input is presented, as would be the case with a normal compiler. Further, by specifying the results to be achieved in the form of logical relationships, the device is able to create the sequence of instructions by converting the relationships into tests comprised within the set of instructions.
In another aspect, where the device is to produce instructions for a target device (such as a digital signal processor (DSP) chip) which has multiple addressing possibilities, the device is arranged to generate plural instruction sequences making use of the addressing modes, and to select one of the instruction sequences, for example to give the highest execution speed.
In one embodiment, the device according to the invention is operable to generate and store a tree defining plural different possible instruction sequences, and to search the stored tree either to find the shortest instruction sequence or to find the instruction sequence which can be expressed most efficiently in an iterated structure.
In another embodiment, the device operates to generate and store only a portion of the tree, utilising iteration whilst generating and storing the tree.
Other aspects and embodiments of the invention are as described or claimed hereafter. The invention will now be illustrated, by way of example only, with reference to the accompanying drawings, in which:
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a block diagram showing schematically the elements of a device according to a first embodiment the invention for generating code sequences, together with a target device for executing the code sequences;
FIG. 2a is a flow diagram showing schematically the process performed by the apparatus of FIG. 1 in a first embodiment of the invention; and
FIG. 2b is a flow diagram showing the operation of a sub routine process called from the process of FIG. 2a to create the contents of the code sequence store;
FIG. 3 shows the structure of one node record in the code store of FIG. 1;
FIGS. 4a and 4b illustrate schematically the contents of the c
REFERENCES:
patent: 5127091 (1992-06-01), Boufarah et al.
patent: 5133077 (1992-07-01), Karne et al.
patent: 5717883 (1998-02-01), Sager
British Telecommunications public limited company
Smith Demetra R.
Trammell James P.
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