Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2006-10-24
2006-10-24
Treat, William M. (Department: 2181)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S217000
Reexamination Certificate
active
07127591
ABSTRACT:
The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor. An instruction control device having instruction storing means for temporarily storing a plurality of decoded instructions yet unissued to an execution unit; wherein the storing means is constituted such that an arranged order of entries of the storing means indicates a decoded order of decoded instructions stored in the entries; wherein that entry, from which the decoded instruction stored therein has been issued, is deleted; wherein information stored in the entries is shifted among the entries such that the entries storing the unissued instructions constitute entries in a continuous order; and wherein a shifting amount between entries is, at the most, equal to the number of instructions which can be simultaneously decoded.
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English translation of Japanese Office Action for JP-10-358985, Notice of Reasons for Rejection dated Feb. 3, 2004.
U.S. Appl. No. 10/747,291, filed Dec. 30, 2003, Takeo Asakawa.
U.S. Appl. No. 10/747,138, filed Dec. 30, 2003, Takeo Asakawa.
Fujitsu Limited
Staas & Halsey , LLP
Treat William M.
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