Patent
1997-02-28
1998-10-06
Harrell, Robert B.
G06F 930
Patent
active
058190589
ABSTRACT:
A system and method for compressing and decompressing variable length instructions contained in variable length instruction packets in a processor having a plurality of processing units is provided that has a compression system with a system for generating an instruction packet containing a plurality of instructions, a system for assigning a compressed instruction having a predetermined length to an instruction within the instruction packet, a shorter compressed instruction corresponding to a more frequently used instruction, and a system for generating an instruction packet containing compressed instructions for corresponding ones of said processing units. The decompression system has a system for storing a plurality of said instruction packets in a plurality of storage locations, a system for generating an address that points to a selected variable length instruction packet in the storage system, and a decompression system that decompresses said compressed instructions in said selected instruction packet to generate a variable length instruction for each of said processing units. The decompression system may also have a system for routing said variable length instructions from the decompression system to each of said processing units.
REFERENCES:
patent: 5057837 (1991-10-01), Colwell et al.
Cardillo Louis A.
Mathieson John G.
Miller Richard G.
Smith Eric R.
Harrell Robert B.
VM Labs, Inc.
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