Instruction completion logic distributed among execution units f

Details Instruction completion logic distributed among execution units f Instruction completion logic distributed among execution units f

1998-06-01

2000-10-17

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712 26, 712205, 712231, 712239, 712240, G06F 900

Patent

active

061346454

ABSTRACT:
Each execution unit within a superscalar processor has an associated completion table that contains a copy of the status of all instructions dispatched but not completed. A central completion table maintains the status of every dispatched instruction as reported by the dispatch unit and the individual execution units. Execution units send finish signals to the completion table responsible for retiring a particular type of instruction. The central completion table retires instructions that may cause an interrupt and instructions whose results may target the same register. The execution units' associated completion tables retire the balance of the instructions and the execution units send instruction status to the central completion table and to each execution unit. This reduces the number of instructions that are retired by the central completion table, increasing the number of instructions retired per clock cycle.

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