Patent
1994-12-20
1996-09-03
Lim, Krisna
395452, 395464, G06F 938, G06F 1208
Patent
active
055532543
ABSTRACT:
A first-in-first-out queue is used to manage instruction sequence execution from an instruction cache in a computer processor. Fields are provided in the queue element structure for not only referencing the correct instruction cache line but also for specifying cache line subsequences and the location of branch instructions so as to cause subsequent execution from other cache lines. The structure is particularly supportive of instruction loops and provides significant performance improvement through the elimination of unnecessary cache line writeovers.
REFERENCES:
patent: 4435756 (1984-03-01), Potash
patent: 4716994 (1987-12-01), Oklobdzija et al.
patent: 4743908 (1990-07-01), Emma et al.
patent: 4847753 (1989-07-01), Matsuo et al.
patent: 4855904 (1989-08-01), Daberkow et al.
patent: 4881163 (1989-11-01), Thomas et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5230068 (1993-06-01), Van Dyke et al.
patent: 5257359 (1993-10-01), Blasco et al.
patent: 5287487 (1994-02-01), Priem et al.
patent: 5317701 (1994-05-01), Reininger et al.
patent: 5327536 (1994-07-01), Suzuki
patent: 5442756 (1995-08-01), Grochowski et al.
Johnson, "Superscalar Microprocessor Design", Prentice-Hall 1991, pp. 71-76 .
Berstis Viktors
Pedersen Raymond J.
Cutter Lawrence D.
International Business Machines - Corporation
Lim Krisna
Vu Viet
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