Instruction buffer device for processing an instruction set of v

Optical communications – Transmitter – Including specific optical elements

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Details

3642599, G06F 930

Patent

active

055985440

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to an instruction decoder and an instruction buffer device in a data processing system. More particularly, the invention relates to a data processing system for processing an instruction set of variable-length instruction code format.


BACKGROUND ART

An instruction set of variable-length instruction code format has a basic segment containing a code identifying type of instructions, and an expanded segment based on the identification in the basic segment. One instruction includes one or more basic segments. The expanded segment's attribute's, such as its presence or absence, length and so forth, are defined by the code in the effective address field contained in the basic segment. The effective address field is inserted immediately after the basic segment by which it is identified. In other words, the basic segment is a portion to be decoded by a decoder, such as a PLA, for the discrimination of instructions. The expanded segment is a data portion generating a displacement value or an immediate value.
FIG. 3(a) is an illustration showing one example of a typical instruction format used in the prior art. This instruction format is frequently established for binary operation. Therefore, discussion will give provided for the binary operation. Basic segments 1 300 and basic segment 2 310 form two basic segments respectively having one unit length (e.g. 2 bytes). Respective basic segments 300 and 310 have effective address fields EA1 504 and EA2 514 respectively identifying source operand and destination operand. Types of instructions are identified by other fields OP1 302 and OP2 312.
The effective address fields 304 and 314 contain encoded information indicating if the operand is a registered, immediate value or data in the memory. When the operand is data in the memory, it also identifies the address calculation method therefor. There are several address calculation methods, for example an absolute address mode identifying an address per se in the expanded segment; a register relative address mode or PC relative address mode adding value of a register or a program counter (PC) to the value of the expanded segment; a SP relative increment mode, in which address calculation and updating of the stack pointer; is performed employing a stack pointer and so forth. It should be noted that the basic segment is provided with a predetermined fixed length per instruction code (the length is variable in different instruction codes).
On the other hand, when the expanded segment is the immediate value, the length is determined according to the operand size. The operand size is assigned as 1 byte, two bytes (half word), four bytes (word) or eight bytes (long word) and so forth. In the case of a one byte immediate value, if the unit length of the instruction code is two bytes, the length becomes insufficient for filling the instruction code. In such a case, extra data (such "O") is added to the upper bite for adapting to the unit length. In the case of memory address identification, the expanded segment is regarded as a displacement value and is used for deriving the address by summing with zero, a register or the PC. In this case, the length of the expanded segment is identified by the effective address field to identify a sixteen bit displacement value, a thirty-two bit displacement value or a sixty-four bit displacement value and so forth. In the case of a SP relative address identification or a register indirect address identification, in which the displacement value is not added, the expanded segment will not be provided. The expanded portion is added immediately after the effective address is filed that identifies the same.
In FIGS. 3(B)-1 through 3(B)- 6, there is illustrated an example of the instruction code string formed with the basic segment and the expanded segment.
In the above-mentioned example, the register is basically formed by the basic segment. The length of the expanded segment arranged following a respective basic segment is illustrated to have the

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