Instruction buffer apparatus of a cache unit

Details Instruction buffer apparatus of a cache unit Instruction buffer apparatus of a cache unit

1978-12-11

1982-01-19

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 930

Patent

active

043120369

ABSTRACT:
A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes an instruction buffer having first and second sections for storing instructions received from main store. Each instruction buffer section includes a plurality of word storage locations, each location having a number of bit positions. A predetermined bit position of each location is used to indicate when an instruction word has been written into the location. Control apparatus coupled to each of the buffer sections is operative to reset all of the word locations to binary ZEROS when a command requesting an instruction block from main store is ready to be transferred thereto. It is set to a binary ONE state when an instruction word is loaded into the location. Instruction buffer ready circuits included within the control apparatus are conditioned by the states of the predetermined bit positions of the locations to generate output signals to the processing unit enabling the transfer of requested instruction words to the processing unit as soon as they are received from main store.

REFERENCES:
patent: 3292153 (1966-12-01), Barton et al.
patent: 3401376 (1968-09-01), Barnes et al.
patent: 3588829 (1971-06-01), Boland et al.
patent: 3699533 (1972-10-01), Hunter
patent: 3928857 (1975-12-01), Carter et al.
patent: 4047244 (1977-09-01), Finkemeyer et al.

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