Instruction and data cache with a shared TLB for split accesses

Details Instruction and data cache with a shared TLB for split accesses Instruction and data cache with a shared TLB for split accesses

1992-04-29

1995-08-08

Harvey, Jack B.

Boots, shoes, and leggings

364DIG1, G06F 1210

Patent

active

054407079

ABSTRACT:
A caching arrangement which can work efficiently in a superscaler and multiprocessing environment includes separate caches for instructions and data and a single translation lookaside buffer (TLB) shared by them. During each clock cycle, retrievals from both the instruction cache and data cache may be performed, one on the rising edge of the clock cycle and one on the falling edge. The TLB is capable of translating two addresses per clock cycle. Because the TLB is faster than accessing the tag arrays which in turn are faster than addressing the cache data arrays, virtual addresses may be concurrently supplied to all three components and the retrieval made in one phase of a clock cycle. When an instruction retrieval is being performed, snooping for snoop broadcasts may be performed for the data cache and vice versa. Thus, for every clock cycle, an instruction and data cache retrieval may be performed as well as snooping.

REFERENCES:
patent: 4953930 (1990-09-01), Ramsey et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5222222 (1993-06-01), Mehring et al.
patent: 5317711 (1994-05-01), Bourekas et al.
patent: 5335335 (1994-08-01), Jackson et al.

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