Instruction address stack in the data memory of an instruction-p

Details Instruction address stack in the data memory of an instruction-p Instruction address stack in the data memory of an instruction-p

1981-06-30

1983-08-16

Thomas, James D.

Boots, shoes, and leggings

G06F 928

Patent

active

043995071

ABSTRACT:
An instruction pipeline for a data processor is disclosed, in which instruction execution is carried out in a sequence of phases which include fetching the instruction from an instruction storage, computing a data storage address from the fetched instruction, accessing the data storage at the computed address to obtain a datum operand, and then carrying out the logical or arithmetic operation on the accessed datum in accordance with the fetched instruction. Branch and stack instructions and return instructions are accommodated by providing a return address stack in the data storage, which stores the next instruction store address to be returned to after a return operation has been completed. Since the instruction address stack in the data storage cannot be directly accessed by the instruction fetching stage of the pipeline until several instruction execution phases have transpired, without degrading the performance of the pipeline, a stack register is provided in the instruction fetch stage of the pipeline which contains a duplicate of the instruction store address presently residing at the top of the instruction address stack. Then when a return instruction is encountered in the instruction fetch stage, the address of the next instruction to be returned to in the instruction storage is immediately available without interrupting the flow in the pipeline. A stack pointer in a stage of the pipeline between the instruction fetch stage and the data store access stage, then takes advantage of unused instruction phases in the pipeline, to cause the data store access stage to read the next available instruction store address from the instruction address stack therein and load it into the stack register in preparation for the next return instruction. Thus, the data storage and instruction stacking function can be shared in the same data storage device which is accessed by an intermediate stage in the multiple phase instruction pipeline without degrading the performance of the pipeline.

REFERENCES:
patent: 3231863 (1966-01-01), Ulfsparre
patent: 3740728 (1973-06-01), Pullen
patent: 3840861 (1974-10-01), Amdahl et al.
patent: 3875391 (1975-04-01), Shapiro et al.
patent: 3900834 (1975-08-01), Casey et al.
patent: 3935563 (1976-01-01), Unger
patent: 3984817 (1976-10-01), Barbour et al.
patent: 4016543 (1977-04-01), Franks et al.
patent: 4025771 (1977-05-01), Lynch, Jr.
patent: 4041462 (1977-08-01), Davis et al.
patent: 4047162 (1977-09-01), Dorey et al.
patent: 4068304 (1978-01-01), Beausoleil et al.
patent: 4109311 (1978-08-01), Blum et al.
patent: 4112489 (1978-09-01), Wood
patent: 4187539 (1980-02-01), Eaton
Ruiz, "An Architecture for Digital Signal Processing," Paper given at the Microdelcon 80 IEEE Computer Society on Mar. 11, 1980.
Braudaway, "Future Signal Processing", IBM Technical Directions, Summer 1980, pp. 25-30.

Affiliated with

Also associated with

Rating

Instruction address stack in the data memory of an instruction-p does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Instruction address stack in the data memory of an instruction-p, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction address stack in the data memory of an instruction-p will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-817819