Instantaneous phase detecting circuit and clock recovery signal

Details Instantaneous phase detecting circuit and clock recovery signal Instantaneous phase detecting circuit and clock recovery signal

1994-09-20

1996-07-16

Chin, Stephen

Pulse or digital communications

Receivers

Angle modulation

375371, 375373, 375375, 375376, H03D 322, H03D 324, H04L 700

Patent

active

055374425

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to an instantaneous phase detecting circuit and a clock recovery signal generating circuit which are incorporated in a differential demodulator for .pi./4-shift QPSK signals.


BACKGROUND ART

As means of digital modulation for the digital mobile communication, the .pi./4-shift QPSK method which carries out the modulation while shifting the phase axis by .pi./4 at a time for each symbol period (two bits, for example) which forms one data unit has been adopted on account of various advantages attendant thereon (literature 1). The differential demodulator of the .pi./4-shift QPSK method which realizes miniaturization of the structure of modulation and economization of the power consumption has been also proposed (literature 2). Communication," No. 2348, written jointly by Yoshihiko Akaiwa and Yoshiki Nagata and presented at the 1985 Consolidated National Meeting of Electronic Communication Society Cordless Telephone," No. B-344, written jointly by Hiroshi Shida, Tsutomu Suda, and Kenzo Urabe and presented at the 1992 Spring General Meeting of Electronic Data Communication Society
FIG. 16 represents a block diagram of the conventional differential demodulator which is disclosed in literature 2.
Now, the differential demodulator for the modulation of a .pi./4-shift QPSK signal will be described below with reference to FIG. 16.
The differential demodulator comprises an input terminal 1, an oscillator 2, an instantaneous phase detecting circuit 3, a phase difference computing circuit 5, a clock recovery circuit 7, a data regenerating circuit 8, a clock recovery signal output terminal 9, and a regenerating data output terminal 10.
The input terminal 1 admits a modulation wave (carrier wave) signal (10, 7 MHz, for example) which has been modulated by the .pi./4-shift QPSK method.
The oscillator 2 generates an electric oscillation which is asynchronous with and substantially equal in frequency to the modulated signal introduced to the input terminal 1.
FIG. 17 represents a block diagram of the conventional instantaneous phase detecting circuit 3. The instantaneous phase detecting circuit 3 is composed of an exclusive OR (hereinafter "EX-OR") circuit 171, a D type flip-flop (hereinafter "DFF") circuit 172, an analog low-pass filter (hereinafter "LPF") 173, an analog/digital converter (hereinafter "A/D converter") 174, and a polarity switching circuit 175.
Now, the operation of the instantaneous phase detecting circuit 3 will be described below with reference to FIG. 18.
FIG. 18a represents phase detection characteristics which have been processed by the EX-OR circuit 171 and the LPF 173. In the diagram, the periods of 0-.pi., 2.pi.-3.pi., and 4.pi.-5.pi. have an upwardly slanting phase detection characteristic and the periods of .pi.-2.pi., 3.pi.-4.pi., and 5.pi.-6.pi. have a downwardly slanting phase detection characteristic respectively to the right. FIG. 18b represents the phase detection characteristics of the DFF circuit 172. In the diagram, the periods of 0-.pi., 2.pi.-3.pi., and 4.pi.-5.pi. have a phase detection characteristic of 1 and the periods of .pi.-2.pi., 3.pi.-4.pi., and 5.pi.-6.pi. have a phase detection characteristic of 0.
The output of FIG. 18a is emitted as it is when the output from the DFF circuit 172 is 1. The output of FIG. 18a is emitted with the sign thereof inverted when the output from the DFF circuit 172 is 0. As a result, a linear phase detection is effected over the periods of from .pi. to 3.pi. and to 2.pi. as shown in FIG. 18c.
The clock recovery circuit 7 is composed of a clock recovery signal generating circuit 71 and a digital phase locked loop (hereinafter "DPLL") 72 as shown in FIG. 19. The clock recovery signal generating circuit 71 is composed of a magnitude comparator 711 and a level setting circuit 712.
FIG. 20 represents the relation between the conventional clock recovery signal and the eye pattern. The term "eye pattern" refers to a figure derived from the loci of a phase difference signal 6 which are described by all the patterns

REFERENCES:
patent: 3971996 (1976-07-01), Motley
patent: 4028626 (1977-07-01), Motley et al.
patent: 4190802 (1980-02-01), Levine
patent: 4881243 (1989-11-01), Whitt
patent: 4912726 (1990-03-01), Iwamatsu
patent: 4928275 (1990-05-01), Moore
Yoshikiko Akaiwa et al., "A Linear Modulation Scheme for Digital Mobile Radio Communications", 1985 IEEE, pp. 965-969.
Hiroshi Nobuta et al., ".pi./4-shift QPSK Differential Demodulator for Digital Cordless Telephone". 1992 Spring Meeting of Electronic Data Communication Society (with an English translation).

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