Instantaneous clock recovery circuit

Pulse or digital communications – Synchronizers

Reexamination Certificate

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Details

C326S003000, C327S367000, C331S1070SL

Reexamination Certificate

active

10324633

ABSTRACT:
A clock recovery circuit (10) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit (10) includes a Josephson transmission line oscillator loop (14) of length 2T, where T is equal to one clock period. First and second data inputs (16, 18) are for injecting a data pulse onto the oscillator loop (14). A pulse generator (24) is for injecting an initial clock pulse onto the oscillator loop (14) that is output as periodic clock signals. An output tap (12) is for outputting the data pulse from one of the first and second data inputs (16, 18), and the periodic clock signals in the absence of the data pulse. When the data pulse is input on one of first and second output taps (32, 34), the clock phase is instantaneously reset.

REFERENCES:
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patent: 5963351 (1999-10-01), Kaplounenko et al.
patent: 6331805 (2001-12-01), Gupta et al.
patent: 6483339 (2002-11-01), Durand et al.
patent: 6486756 (2002-11-01), Tarutani et al.
V. Kaplunenko, “Noise consideration in RSFQ circuits,”PHYSICA C, North Holland Publishing, Amsterdam, NL, vol. 372-376, Aug. 2002, pp. 119-123, XP004375373 ISSN; 0921-4534.
Office Action issued from European Patent Office issued on Nov. 30, 2005 for the corresponding European patent application No. 03 023 895.0-2415.
V. Kaplunenko, V. Borzenets, and N. Dubash, “Superconducting single flux quantum 20 Gb/s clock recovery circuit,”Applied Physics Letters, Jul. 7, 1997, vol. 71, Issue 1, pp. 128-130.

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