Pulse or digital communications – Synchronizers
Reexamination Certificate
2007-01-30
2007-01-30
Tran, Khanh (Department: 2611)
Pulse or digital communications
Synchronizers
C326S003000, C327S367000, C331S1070SL
Reexamination Certificate
active
10324633
ABSTRACT:
A clock recovery circuit (10) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit (10) includes a Josephson transmission line oscillator loop (14) of length 2T, where T is equal to one clock period. First and second data inputs (16, 18) are for injecting a data pulse onto the oscillator loop (14). A pulse generator (24) is for injecting an initial clock pulse onto the oscillator loop (14) that is output as periodic clock signals. An output tap (12) is for outputting the data pulse from one of the first and second data inputs (16, 18), and the periodic clock signals in the absence of the data pulse. When the data pulse is input on one of first and second output taps (32, 34), the clock phase is instantaneously reset.
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Northrop Grumman Corporation
Posz Law Group , PLC
Tran Khanh
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