Instant-acquisition clock and data recovery systems and...

Pulse or digital communications – Receivers – Angle modulation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C375S355000

Reexamination Certificate

active

07929644

ABSTRACT:
Methods and systems for recovering clock and data in data streams communicated over serial communications links. An exemplary serial communications receiver system includes a line receiver configured to receive a data stream from a serial communications link and an instant-acquisition clock and data recovery circuit coupled to the line receiver. The instant-acquisition clock and data recovery circuit includes a time interval detector and a sampling clock selector. The time interval detector is operable to sample the data stream received by the line receiver according to a multi-phase set of sampling clocks. The sampling clock selector is operable to designate one of the sampling clocks of the multi-phase set of sampling clocks as a recovered clock, based on a data transition in the received data stream detected by the time interval detector. The clock selector is configured to designate the sampling clock as the recovered clock independent of data transitions in the data stream that may have occurred prior to the data transition detected by the time interval detector.

REFERENCES:
patent: 7142623 (2006-11-01), Sorna
patent: 2003/0161430 (2003-08-01), Sou
patent: 2004/0036516 (2004-02-01), Kim
patent: 2005/0091559 (2005-04-01), Vining
patent: 2005/0238126 (2005-10-01), Ribo et al.
patent: 2005/0254456 (2005-11-01), Sakai et al.
patent: 1 009 125 (2000-06-01), None
patent: 1 306 999 (2003-05-01), None
M. Ramezani et al., “Jitter analysis of a PLL-based CDR with a bang-bang phase detector,” 2002 45th Midwest Symposium in Circuits and Systems, Aug. 4-7, 2002, p. 393-396, vol. 3.
M. Ramezani et al., “An improved bang-bang phase detector for clock and data recovery applications,” 2001 IEEE International Symposium on Circuits and Systems, May 6-9, 2001, pp. 715-718, vol. 1.
Park, Jun-Young et al., “A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method”, IEICE Trans. Fundamentals, vol. E83-A, No. 6, Jun. 2000, pp. 1100-1105.
Kitazawa, Masakazu et al., “A Bit Synchronization Technique for PDS Optical Subscriber Loop Systems”; Telecommunications Division, Hitachi, Ltd. Yokohama, Japan; 1991, pp. 8.2-1 through 8.2-10.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Instant-acquisition clock and data recovery systems and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Instant-acquisition clock and data recovery systems and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instant-acquisition clock and data recovery systems and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2666163

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.