Cleaning and liquid contact with solids – Processes – For metallic – siliceous – or calcareous basework – including...
Reexamination Certificate
2000-09-08
2003-06-10
Stinson, Frankie L. (Department: 1746)
Cleaning and liquid contact with solids
Processes
For metallic, siliceous, or calcareous basework, including...
C134S076000, C134S083000, C118S423000, C118S428000, C118S503000
Reexamination Certificate
active
06576065
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of microelectronics. It relates more particularly to the field of installations for treating wafers of materials used as substrates for the fabrication of microelectronic components and in particular chemical treatment installations.
BACKGROUND ART
To be more precise, the present invention relates to the field of installations and methods for treating and manipulating wafers, in particular in the context of methods of manipulating wafers without using a cassette, which type of installation is often referred to as a “cassetteless” installation. It is nevertheless also directed to certain manipulations using cassettes that receive wafers.
The document U.S. Pat. No. 5,657,879 discloses a cassette for receiving wafers including plates for adjusting the capacity of the cassette and sleeves, also in the form of cassettes, for adapting the cassette to receive wafers with different dimensions.
The document DE 45 00 205 discloses a cassette for receiving wafers including an adaptor for receiving wafers with different dimensions.
Chemical treatment of wafers for microelectronics generally necessitates the immersion of the wafers in baths of chemical products, some of which are corrosive.
In cassetteless installations for manipulating and treating wafers, the wafers are initially disposed in batches of 25 in a manipulation and storage cassette, for example, and are removed from the cassettes and immersed successively in different chemical baths. Between the baths, the wafers are grasped by special combs in order to be transferred from one chemical bath to another. In each bath the wafers are disposed on wafer supports which are intended to remain permanently in the chemical bath.
The wafers are deposited on wafer supports specific to each tank and the combs do not remain in the tanks during treatment. This type of installation enables the chemical treatment to be optimized by adapting the wafer supports in each tank. The wafer supports can have a very small volume and surface area to interfere with the treatment as little as possible.
This type of installation avoids contamination of the baths by the chemical products which remain on the baskets or cassettes if baskets or cassettes are used to transfer wafers from one tank to another. What is more, there can be a multiplicity of transfer combs, for example, to avoid the combs being dipped successively into chemically incompatible baths. They can also be rinsed while the wafers are undergoing chemical treatment. However, this type of installation is unable to treat several sizes of wafers using the same system. The comb system is already difficult to adjust mechanically to guarantee proper holding of wafers of a single type, and therefore there is no question of achieving an adjustment enabling satisfactory holding of wafers of several types, i.e. several sizes.
SUMMARY OF THE INVENTION
The present invention provides an economic way of treating more than one type of wafer in the above type of installation.
This is achieved by an installation for treating wafers of a material used as a substrate for microelectronics, the installation comprising:
a tank adapted to contain a treatment bath and provided with wafer support means, preferably in the form of a wafer support device that is adapted to receive at least one wafer of a first size;
holding means, preferably in the form of a grasping element that is adapted to grasp each first size wafer to place it in the tank and withdraw it therefrom; and
a support that is adapted to receive at least one wafer of a second size less than the first size, which support has a geometry such that it can be grasped directly by the holding means and received by the wafer support means of the tank.
Thus, even if an installation according to the invention is dedicated to treating wafers of a first size, it is possible to effect chemical treatment of wafers of a second size smaller than the first size.
BRIEF DESCRIPTION OF THE INVENTION
For example, if the installation is dedicated to treating 20 cm diameter wafers, the grasping means, for example combs, are adjusted for that diameter and the tanks are provided with wafer supports adapted to receive wafers of that size.
The installation can nevertheless also be used to treat 10 cm diameter wafers, for example, because all that is required is to place the 10 cm diameter wafers in a support having a geometry such that it can be grasped by the combs.
That geometry is advantageously determined by manipulator plates whose shape is similar to that of a wafer of the first size, i.e. has a diameter of 20 cm, in the example described above.
It is even more advantageous for the support to include two manipulator plates joined together by strips adapted to hold a batch of wafers of the second size, either directly or through the intermediary of a cassette.
In another aspect, the invention proposes a method of treating wafers of materials used as substrates for microelectronics, including a step of employing holding means originally designed to grasp at least one wafer of a first size and to immerse each wafer in a treatment bath contained in a tank provided with wafer support means adapted to receive at least one wafer of said first size, characterized in that it alternately includes a step of using the same holding means to grasp a support adapted to receive at least one wafer of a second size, less than the first size, and to immerse the second size wafers in the treatment bath by depositing said support in said tank so that it cooperates with said wafer support means.
REFERENCES:
patent: 5301700 (1994-04-01), Kamikawa et al.
patent: 5657879 (1997-08-01), Anderson et al.
patent: 5853496 (1998-12-01), Honda
patent: 6001191 (1999-12-01), Kamikawa et al.
patent: 6158449 (2000-12-01), Kamikawa
patent: 6199564 (2001-03-01), Yokomizo
patent: 43 00 205 (1994-07-01), None
Perrin Joseph
S.O.I.Tech Silicon On Insulator Technologies
Stinson Frankie L.
Winston & Strawn
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