Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2001-07-30
2004-09-14
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S765010, C345S204000
Reexamination Certificate
active
06791350
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an inspection method for an array substrate used in a liquid crystal display apparatus and an inspection device for the same, more particularly to a disconnection inspection method for storage capacitor lines on a TFT array substrate and a disconnection inspection method for the same.
2. Prior Art
As shown in FIG.
8
(
a
), in a thin film transistor (TFT) array substrate, signal lines
15
and gate lines
21
are wired in the form of matrix on a glass substrate while crossing to each other in an electrically nonconductive state, and TFTs
22
are arranged in the vicinity of cross portions thereof. The above-described gate line
21
and signal line
15
are respectively connected to a gate and a source of a TFT
22
. A transparent electrode (ITO) is connected to a drain of the TFT
22
. A storage capacitor electrode
25
is arranged so as to be opposite to a specified portion
23
of the transparent electrode, and a storage capacitor (Cs)
24
is constituted of the specified portion
23
of the transparent electrode and the storage capacitor electrode
25
. In the case of a storage capacitor system, the storage capacitor electrode
25
is connected to storage capacitor drives circuit through a storage capacitor line (hereinafter referred to as a Cs line)
13
. An arrangement of the respective lines and electrodes or the like described above on the TFT array substrate is performed by repeating a patterning process on the glass substrate.
In recent years, a length of each of the above-described lines has become longer owing to a larger screen of the liquid crystal display apparatus, and each of the above-described lines has become thinner owing to high definition of the liquid crystal display apparatus. This results in a higher probability of occurrence of defective articles due to a line disconnection or the like, when the above-described patterning process forms each line. Therefore, an inspection of the TFT array substrate is performed to prevent the defective articles from entering the subsequent manufacturing process in the case where the defective articles occur. For the inspection, a TFT array tester generally available in a market is used. The TFT array tester is capable of inspecting a disconnection (open circuit), a short circuit and a defective resistance of each line, a pixel defect or the like.
In the disconnection inspection of each line by using the above-described TFT array tester, using the above-described TFT array tester has not performed the disconnection inspection for the Cs line
13
. This is because the Cs line
13
is short and defects of the Cs line
13
due to disconnection are difficult to be detected even if a lighting test is executed for a small panel of 12 inch diagonal or less using the storage capacitor system, and because a structure shown in FIG.
9
(
a
) without the Cs line
13
(drive capacitor system) is adopted in most liquid crystal display panels of 14 inch diagonal or larger. Since this drive capacitor system does not wire the Cs line
13
, there are advantages that the probability of occurrence of defective articles is reduced and an aperture ratio of the liquid crystal display apparatus is improved.
However, when the liquid crystal display has higher definition and a larger size, wiring of the gate line
21
becomes longer and a line width thereof becomes thinner, resulting in a larger resistance of the wiring. Moreover, since the number of the signal lines
15
is large, capacitance at a cross portion of the signal line
15
and the gate line
21
increases. As a result, a load to a gate driver outputting a gate drive signal becomes larger. Furthermore, in the drive capacitor system, since the storage capacitor electrode
25
of the storage capacitor
24
is connected to the gate line
21
of a front or rear step thereof, both of the gate signal and the signal to the storage capacitor electrode
25
exist mixedly in the gate line
21
, and a quantity of charges that can be stored in the storage capacitor
24
is relatively small in comparison with the storage capacitor system.
Because of the reason described above, recently in the liquid crystal display panel of 14 inch diagonal or larger, the storage capacitor system using the Cs line
13
as shown in FIG.
9
(
b
) has been increasingly adopted. Therefore, when the storage capacitance system is used in the liquid crystal display panel of 14 inch diagonal or larger, the Cs line
13
is included. Accordingly, if the Cs line
13
is disconnected, the disconnection of the Cs line
13
is detected by the lighting test. However, the lighting test is performed after the liquid crystal display panel is assembled. Therefore, it is more waste less and preferable that the disconnection of the Cs line
13
be detected at a stage where TFT array substrates are manufactured, and that defective TFT array substrates are not allowed to enter the subsequent process.
The TFT array tester inspecting a disconnection, a short circuit and a defective resistance of each line, a pixel defect or the like of the TFT array substrate cannot detect the disconnection of the Cs line
13
. The tester supplies a pulse signal Vd as shown in
FIG. 10
to the signal line
15
while supplying a constant voltage Vcs to the Cs line
13
. By supplying the constant voltage Vcs to the Cs line
13
, the voltage Vcs is applied to the storage capacitor electrode
25
. Note that, in the above-described pulse signal Vd, since the falling of the pulse signal Vd occurs after the gate signal is turned off, and does not have a relation to a potential difference in the storage capacitor
24
, the pulse signal Vd falls in an optional time.
And, as shown in
FIG. 10
, the gate signal is applied from the gate line
21
to the TFT
22
at the time t
0
to turn the TFT
22
to an ON state, thus the pulse signal Vd is applied from the signal line
15
to the specified portion of the transparent electrode
23
of the storage capacitor
24
having a capacitance of C. Moreover, at the time t
1
, the TFT
22
is turned to an OFF state by turning off the gate signal. When the voltage of the pulse signal Vd at this time is set as Vd
1
, the voltage at the specified portion of the transparent electrode
23
becomes Vd
1
. With regard to a potential difference between the specified portion of the transparent electrode
23
of the storage capacitor
24
and the storage capacitor electrode
25
after the time t
1
, a difference between the voltages Vcs and Vd
1
, is maintained, and a quantity of charges Q
1
stored in the storage capacitor
24
becomes C coulomb (Vcs-Vd
1
). Thereafter, the gate signal is applied to the TFT
22
to turn the TFT
22
to an ON state. Then, the quantity of charges Q
1
stored in the storage capacitor
24
is detected by a reading circuit of the TFT array tester.
However, since the voltage Vcs supplied to the Cs line
13
is a constant voltage, when the pulse signal Vd from the signal line
15
is not applied to the storage capacitor
24
, the voltage of the specified portion of the transparent electrode
23
is 0V, and the potential difference between the specified portion of the transparent electrode
23
of the storage capacitor
24
and the storage capacitor electrode
25
becomes Vcs. At this time, a quantity of charges Q
2
stored in the storage capacitor
24
becomes CVcs coulomb, and the quantity of charges Q detected by the TFT array tester becomes CVd
1
, coulomb that is a difference between Q
2
and Q
1
. Therefore, this indicates that the quantity of charges Q is determined by writing voltages from the storage capacitor
24
and the signal line
15
, and that an influence of the disconnection of the Cs line
13
is not considered.
In addition, Japanese Patent Laid-Open No. Hei 11(1999)-84420 discloses a detection method, in which resistance of each type of line is calculated by measuring a voltage and a current in each kind of line and a disconnection or a short circuit is detected by the calculated resistance values. However in t
Cuneo Kamand
Nguyen Jimmy
Scully Scott Murphy & Presser
Trepp, Esq. Robert M.
LandOfFree
Inspection method for array substrate and inspection device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Inspection method for array substrate and inspection device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Inspection method for array substrate and inspection device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3234808