Classifying – separating – and assorting solids – Sorting special items – and certain methods and apparatus for... – Condition responsive means controls separating means
Reexamination Certificate
2000-05-23
2001-09-25
Nguyen, Tuan N. (Department: 3653)
Classifying, separating, and assorting solids
Sorting special items, and certain methods and apparatus for...
Condition responsive means controls separating means
57, 57
Reexamination Certificate
active
06294747
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains to the field of automatic handling equipment. More particularly, it pertains to a high speed machine for loading, visually inspecting, and classifying surface mount passive components (a type of miniature electronic component) using extreme care and particular accuracy.
2. Description of the Prior Art
As our society matures, the electronic industry continues to burst forth with new and more diversified products and services. More uses are being found for computers and computer components. As these uses expand, there is constant pressure to reduce the size of computers, their components and the circuitry involved. As an example, the age-old capacitor has shrunk from a cigarette-size cylinder with wires extending from the ends thereof to tiny ceramic devices called “MLCC” (Multi-Layer Chip Capacitors) and “SURFACE MOUNT PASSIVE COMPONENTS”, smaller than a grain of rice with metal terminations at the ends thereof. At the present time, these “chips” as they are generically known, have been reduced in size to a ceramic device having overall dimensions of 0.040×0.020—0.020 inches. Fifty of them could be set side-by-side within an inch. These chips come in a range of sizes as shown in FIG.
1
.
In addition to the pressure to make these components smaller, there is similar pressure to process them faster. In processing chips, numerous electronic tests must be conducted on each to classify them according to their electronic properties. Some of these tests are described in detail in U.S. Pat. No. 5,673,799 but can be summarized as a Dissipation Factor test, a Capacitance Test, a Flash Test, and an Insulation Resistance Test. New tests are constantly being established so that the battery of tests to be conducted on these miniature chips continues to grow.
In order to make processing chips more efficiently, it is necessary to eliminate visibly flawed chips from the electronic testing phase so that overall processing time is reduced and electronic testing is conducted only on those chips that can fulfill all the requirements of the circuitry. Examples of such visually observable flaws are delamination of the dielectric body, cracks in the chip's exterior, divots from the corners or along a marginal edge, or flaws in the metal termination such as smears, spillovers, and unacceptable waviness in the termination paste. These flaws are known to cause changes in the desired electric characteristics of the chip such that they may be segregated for use in less demanding environments.
Accordingly, a movement is underway to subject pre-tested chips to visual checks so that damaged chips can be segregated for use in other areas of the industry, where such flaws can be tolerated, thus making the subsequent electrical testing more efficient and thereby increase handling rates and reduce the costs of producing an acceptable high quality chip. To perform the visual test in an efficient manner, it is necessary to process them at high throughput rates and yet be gentle in handling them. Rates approaching 75,000 per hour are being sought. This means that one machine must visually inspect twenty to twenty-one miniature ceramic chips each second. To do so requires a machine that can handle a huge amount of chips in an efficient manner. However, any overt force applied to the chips, such as crowding them in a confined area or dropping them a distance onto a flat surface will produce its own brand of flaws, usually in the form of cracks in the chip.
SUMMARY OF THE INVENTION
This invention is a visual inspection machine for miniature multilayer capacitor chips (chips) comprising a rotating loader wheel of finite thickness defined by an outer rim for accepting the 3-dimension miniature chips on the rim; a first inspection means, spaced-apart from the loader wheel; for visually inspecting the single outer surface of the chip during its travel on the wheel, a rotating transfer wheel defined by an outer marginal edge, arranged planar to the loader wheel and in coordinatedjuxtaposed movement therewith, for relocating the chips from the rim of the loader wheel to the outer marginal edge of the transfer wheel following passage beyond the first inspection means; a second inspection means, spaced-apart from the transfer wheel, including television caneras and possibly the use of mirrors, LEDs, strobe lights, prisms, and the like, for visually inspecting the other surfaces of the chip during its travel on the transfer wheel, a computer for locating and following each chip from its initial location on the loader wheel through its passage on the transfer wheel to identify it as a visually inspected and “passed” or “failed” chip, as well as classifying the “failed” chips as to their specific failure, i.e., delamination, chipped, smeared termination, etc.; a first pneumatic means for removing rejected “failed” chips (either as a whole group or by specific failure) from the outer marginal edge of the transfer wheel, for capture in one or more bins; and, a second pneumatic means for removing visually accepted chips from the outermarginal edge of the transfer wheel for capture in one or more other bins.
Other features of the invention include the ability to handle and visually inspect one of the smallest chips, known in the industry as an “0402” chip, having external dimensions as small as 0.040×0.020×0.020 inches, the ability to handle throughputs as high as 100% of maximum loading capability of the machine, moving these small chips delicately so that handling by the machine does not result in damage to the chips, being able to visually check a part of or the full exterior of the chip by placing the chip in only two positions, delicately removing the chips from the machine into sorted bins, and very safely and efficiently insuring only visually acceptable chips reach the “good” bin. Still further, the bins are of a unique design whereby the bottoms thereof onto which the chips fall are angled to provide an inclined surface thus preventing any damage or further damage to the chips during their passage from the transfer wheel into the appropriate bin.
Accordingly, the main object of this invention is a machine which performs a fast and safe visual inspection of these miniature ceramic chips at high throughput rates using delicate handling technique, to insure the chips will not be degraded through handling. Other objects of this invention include a machine which may inspect up to all six sides of a chip, using only two positions of the chip during inspection; a machine that insures against surface damage of a chip during all phases of inspection and classification phases of the testing; a machine that provides foolproof classification and collection of chips that pass inspection into a single location; and, a machine that can handle upwards of 70,000 chips per hour in the visual inspection phase.
These and other objects of the invention may be determined by reading the description of the preferred embodiments along with the drawings attached hereto. The scope of protection sought by the inventor may be gleaned from a fair reading of the claims that conclude this specification.
REFERENCES:
patent: 4354602 (1982-10-01), Miyoshi et al.
patent: 6025567 (2000-02-01), Brooks
patent: 427611 (1991-05-01), None
patent: 2590811 (1987-06-01), None
patent: 2-193813 (1990-07-01), None
Braden Denver
de Vera Romulo V.
Hawkes Malcolm Vincent
Liu Donald
Electro Scientific Industries Inc.
Murphey, Esq. John J.
Nguyen Tuan N.
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