Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-12-28
2002-08-27
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S203000, C029S830000, C029S852000, C228S180220, C427S097100
Reexamination Certificate
active
06441319
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to multi-layer substrates and, more particularly, to a technique for facilitating connection of signal tracks and impedance matching in multi-layer substrates.
BACKGROUND OF THE INVENTION
The present state of the art involves the use of vias, which are holes plated with metal, to connect signal tracks on different layers in multi-layer substrates. Such vias, when used with high-speed signals such as digital signals, lead to problems such as impedance mismatches and cross-talk to adjacent signal tracks on any layer and to adjacent vias.
The extent of the problem depends upon the type of via used and related size and material characteristics. There are three basic via classifications, namely:
a) Super-Via—extends all of the way through the substrate;
b) Blind Via—visible from outside of the substrate on one side only (a microvia is a type of blind via which is typically fabricated by laser drilling and is smaller than mechanically fabricated blind vias); and
c) Buried Via—not visible from outside of the substrate.
The high frequency performance of vias depends mainly on a number of geometric features such as length of the plated-through hole, and diameter of the plated-through hole. The high frequency performance of vias further depends on the dielectric constant of the substrate dielectric layers. Other features that impact the high frequency performance of vias include the number, size, and shape of metallic pads used on the via and the number, size, and shape of the clearance holes, also called antipads, used where the plated-through hole must penetrate the metal reference planes (eg., ground or power planes). Performance is also impacted by the location and orientation of the electrical connections between the via structure and the signal layers, eg., the angle between connecting layers and the physical separation between connected signal layers and the presence of extraneous via projections beyond the segment of the via that carries the signal between the connected layers. These projections as transmission line stubs which exacerbate the impedance match.
Ideally, the via structure between the connected layers should have a uniform controlled impedance which matches that of the signal tracks that it connects together, and also the via should not project beyond the connected region (no stubs allowed). Conventional vias inherently do not have a uniform controlled impedance, since the proximity of the via cylindrical outer surface to adjacent ground and power reference plane surfaces varies along the length of the via. Also, metal pads which are used to bridge the connection from a signal track to the periphery of the via cylinder and which also typically appear on primary and secondary substrate layers also act as lumped capacitive loads on the via, worsening the uniformity of the via impedance. As a result, the high-speed circuit design of conventional vias only attempts to control the average value of the via impedance over its length, which limits the high frequency/high speed performance of these structures. In many applications, layout and design constraints prevent even this from being attained. For example, in dense wiring areas of the substrate, the clearance holes around the vias (antipads) simply cannot always be increased in diameter sufficiently to increase the impedance to typically desired values of 50 Ohms. The limit is reached when the antipads blend together to create a large slot in the reference planes which is normally unacceptable because signal layers routed over such a slot will experience a serious impedance discontinuity.
Another constraint is that the via diameter reaches a lower limit determined by the maximum aspect ratio (defined as the length to diameter ratio of the drilled via holes) of the PCB fabrication technology which is typically in the range of 7:1 to 10:1 for supervias.
In conventional via structures, stubs can only be avoided by the use of blind or buried vias, or by controlled depth drilling to remove the unused portions of the via. All of these approaches incur a significant cost penalty.
Cross-talk associated with conventional vias can be from via to signal layer or via to via in high density layouts. Problems can occur if a combination of large via size and very high frequency or speed occurs. Such crosstalk problems can mainly be solved by increasing the spacing between affected conductors, as the insertion of a shielding conductor is not normally practicable or effective in high density wiring environments.
In view of the foregoing it would be desirable to provide a technique for connecting signal layers in a multi-layer substrate which overcomes the above-described inadequacies and shortcomings. More particularly, it would be desirable to provide a technique for connecting signal layers and avoiding impedance mismatching in an efficient and cost effective manner.
SUMMARY OF THE INVENTION
According to the present invention, a method for connecting signal tracks on different layers in a multi-layer substrate is provided. The method comprises the steps of forming an opening in the substrate through at least two layers of the substrate and inserting a first component into the opening, the first component comprising a dielectric block and a conductive layer bonded to the dielectric block extending through the substrate so as to connect at least two signal tracks on different layers. The method additionally comprises bonding the first component to the substrate.
In accordance with other aspects of the present invention, a multi-layer substrate is provided that comprises a plurality of signal tracks on different layers and an opening formed through at least two layers of the substrate. A first component is inserted in the opening. The first component comprises a dielectric block, wherein the placement of the first component creates a path intersecting with at least two signal tracks on different layers. A conductive layer is bonded to the dielectric block to create a signal layer connecting the two signal tracks on different layers.
In accordance with further aspects of the present invention, a system for connecting signal tracks on different layers within a substrate is provided. The system comprises a first passive component insertable into a substrate. The first passive component is shaped to contact at least two signal tracks on different layers of the substrate. The system further comprises additional material shaped to be positioned adjacent the first inserted component so as to create an electrical conductor path between the additional material and the first inserted component intersecting with the at least two signal tracks on different layers.
The present invention will now be described in more detail with reference to exemplary embodiments thereof as shown in the appended drawings. While the present invention is described below with reference to preferred embodiments, it should be understood that the present invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present invention as disclosed and claimed herein, and with respect to which the present invention could be of significant utility.
REFERENCES:
patent: 5419038 (1995-05-01), Wang et al.
patent: 5590029 (1996-12-01), Estes
patent: 5659953 (1997-08-01), Crane et al.
patent: 6181219 (2001-01-01), Gailus et al.
Goulette Richard R.
Handforth Martin R.
Kwong Herman
Meier Rolf G.
Hunton & Williams
Nortel Networks Limited
Paladini Albert W.
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