Insert testing system

Details Insert testing system Insert testing system

1999-04-14

2001-11-06

Nguyen, Vinh P. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S755090, C324S765010

Reexamination Certificate

active

06313650

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to patterning techniques in the microelectronics industry. More particularly, the present invention relates to photolithographic techniques for preserving a substantially uniform layer upon a substrate topology. In particular, the present invention relates to methods of patterning and etching trenches and pits and forming a continuous layer that electrically communicates out of the trench or pit to an upper surface. The method is carried out after a manner that avoids nonuniformities of the continuous layer that communicates out of the trench or pit to an upper surface.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above. The term semiconductor substrate is contemplated to include such structures as silicon-on-insulator, silicon-on-sapphire, and the like.
In the field of chip packaging, a goal for those skilled in the art is to miniaturize the chip package, such as in chip scale packages (CSP) where the package itself is only about 1-2 times the size of the chip. Various methods have been proposed to eliminate wire bonding and to achieve lead on chip (LOC) wiring as a means of decreasing chip packaging size. Traditionally, connections have been achieved by connecting a bonding wire from a bonding pad on the chip to a lead finger. However, wire bonding is time consuming and costly, particularly as the number of inputs and outputs from a single chip increases.
As integrated circuit technology advances, other methods of connecting input and output from a chip to the external world must be explored to facilitate miniaturization. New packages such as CSP, ball grid array (BGA) packages and flip chips have all been developed as methods of miniaturizing chip packages. In a BGA, solder balls, also called solder bumps, or electrically conductive prominences, are generally intended to all be of substantially the same size. For example, the solder balls may be about 0.3 to 0.4 millimeters in diameter and contact the die bond pads through the bottom of the package surface. Generally an array of electrical contacts congruent to the solder ball array is to be found on a circuit board to which the package containing the solder balls is to be mounted. The solder balls individually contact their corresponding pads on a printed circuit board (PCB). In order to assure adequate contact, solder paste is often required to accommodate for variations and discrepancies between solder ball sizes and solder ball locations. After contact, the circuit board and the chip are placed in a solder reflow furnace under conditions sufficient to cause the solder ball to reflow and coalesce within the solder paste in order to form an adequate electrical connection.
Conventionally, solder bump reflowing is used to mount a chip or chip package onto a PCB. A degree of dimensional variation occurs with solder bumps in the prior art. Reliability in the mounting and electrical connection of integrated circuit packages to their mounting boards is important because the solder joints between the contacts of the chip and those of the PCB are highly difficult to visually inspect and non-destructively test once the chip is in place on the PCB. Although statistical methods of quality control along with destructive testing methods must be relied upon to provide confidence that reliable electrical connections are being made, more effective methods are being sought.
Prior to mounting of integrated circuit packages to their mounting boards, it is important and often indispensable that testing of the chip package is carried out. In particular, testing under adverse conditions, called “burn-in” must be conducted. Testing must be carried out before the final mounting of a chip package to a PCB. Accordingly, testing structures have been made that are electrically conductive and that are configured to match the BGA of the chip package.
As design efforts that emphasize miniaturization continue, the making of a testing structure that receives and electrically connects with the bumps of a BGA package become increasingly challenging. Formation of a testing array can be carried out according to standard photolithographic techniques. With miniaturization, however, fabrication problems arise.
FIG. 1
is an elevational cross-section view of a semiconductor structure
10
. Semiconductor structure
10
comprises a substrate
12
, a metal layer
14
, and a masking layer
16
according to the prior art. It can be seen that masking layer
16
covers portions of metal layer
14
including coverage of an upper surface
24
of substrate
12
. Masking layer
16
is also over a pit surface
26
of substrate
12
within a pit
20
into which metal layer
14
has been formed.
Due to various processing parameters, a breach
18
can be seen in masking layer
16
. Breach
18
may be formed due to the presence of a sharp comer
22
on an upper surface
24
of substrate
12
. Sharp comer
22
causes substantial thinning of masking layer
16
during formation thereof. Additionally, breach
18
may be caused by mechanical action of a process performed upon masking layer
16
, exacerbated because of the thinness of masking layer
16
at sharp corner
22
.
Where metal layer
14
is used as an electrical contact for testing a BGA upon a chip package or the like, masking layer
16
is patterned in order to achieve a substantially continuous electrically conductive structure comprising metal layer
14
. During CSP or flip chip testing, through electrical conductivity of a BGA, it is preferable that metal layer
14
within pit
20
be in uninterrupted electrical communication with other portions of metal layer
14
that form metal lines (now shown). Patterning of masking layer
16
is carried out in order to form distinct and separate electrical contacts within pit
20
that also run along upper surface
24
of substrate
12
.
FIG. 2
illustrates the prior art result of thinning of masking layer
16
(not shown) due to the presence of sharp corner
22
after a patterning etch of metal layer
14
to form metal lines. Semiconductor structure
10
includes substrate
12
and a broken metal line
28
that was formed from metal layer
14
. Typically, there is a dielectric between substrate
12
and metal layer
14
, particularly where substrate
12
may be electrically conductive or semiconductive. Broken metal line
28
exists both upon upper surface
24
of substrate
12
and upon pit surface
26
of pit
20
within substrate
12
. An individual solder ball, bump, or the like is to be inserted within pit
20
during testing. Problematically, no electrical contact can be made from broken metal line
28
within pit
20
to upper surface
24
of substrate
12
. Consequently, no electrical testing of the chip package can be carried out due to the existence of a breach
30
in broken metal line
28
. Additionally, where breach
30
is not formed during fabrication, breach
30
may form during use, where metal layer
14
may have been thinner near sharp corner
22
due to thinning of masking layer
16
instead of the formation of a breach thereof.
What is needed in the art is a method of forming a BGA testing receiver that does not suffer from the problems of the prior art. What is also needed in the art is a method of forming a testing package for a semiconductor chip package that resists formation of broken
SUMMARY OF THE INVENTION
T

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