Inrush current suppressing power supply

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

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323299, 323908, 363 49, 363 50, G05F 500

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active

056191278

ABSTRACT:
Main power supply circuit includes an inrush current suppressing circuit serially connected between its rectifying circuit and a load, this inrush current suppressing circuit being composed of a current limiting resistor and an FET switch that is serially connected to this resistor. An auxiliary power supply circuit provides power for a control circuit of the main power supply circuit, and, after the power supply switch is closed, a delay circuit monitors rise of a charge voltage of a smoothing capacitor within the main power supply circuit as well as rise of control circuit voltage of the auxiliary power supply circuit and establishes a delay time. After the elapse of the delay time, the FET switch is turned ON and the inrush current suppressing circuit is closed. The inrush current suppressing circuit is then short circuited within a short time period and the load operation is continued. Even if the power supply is cut and then reclosed within a short time interval, a delay interval is interposed without fail and the inrush current suppressing circuit closed, thereby preventing heat damage.

REFERENCES:
patent: 4494064 (1985-01-01), Harkness
patent: 4866590 (1989-09-01), Odaka et al.
patent: 5283707 (1994-02-01), Conners et al.
patent: 5341279 (1994-08-01), Yamada

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