Input-voltage detector circuit for CMOS integrated circuit

Details Input-voltage detector circuit for CMOS integrated circuit Input-voltage detector circuit for CMOS integrated circuit

1985-08-19

1987-11-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307350, 307356, 307576, 307594, H03K 5153, H03K 1730, H03K 17284, G11C 800

Patent

active

047091720

ABSTRACT:
An input-voltage detector circuit for increasing the functionality of a CMOS integrated circuit without requiring an increase in the number of pins or terminals of the integrated circuit includes an N-channel enhancement-mode transistor having its source terminal and substrate region electrically connected to the input of the circuit. A ground-voltage potential is applied to the gate terminal of the N-channel enhancement-mode transistor and a load element is connected between the drain terminal of the N-channel enhancement-mode transistor and the positive-voltage power supply node of the circuit. The drain terminal of the N-channel enhancement-mode transistor is further connected to a buffer stage which provides the output of the circuit. The input-voltage detector circuit detects when a voltage more negative than ground by a predetermined level is applied to the input of the detector circuit. Thus, a circuit is provided which detects the application of an unusual voltage condition at its input; the output of the circuit can be utilized by other on-chip logic to cause the integrated circuit to function differently than under usual conditions.

REFERENCES:
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patent: 4064405 (1977-12-01), Cricchi et al.
patent: 4140930 (1979-02-01), Tanaka
patent: 4418291 (1983-11-01), Watson, Jr.
patent: 4418292 (1983-11-01), Cserhalmi et al.
patent: 4453094 (1984-06-01), Peil et al.
patent: 4658156 (1987-04-01), Hashimoto

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