Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-04-29
2001-02-27
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S328000, C327S333000
Reexamination Certificate
active
06194944
ABSTRACT:
FILED OF THE INVENTION
The present invention relates to input structures and, more particularly, to input structures for protecting Integrated Circuits.
BACKGROUND OF THE INVENTION
Input structures for protecting the gate oxide of MOS (Metal Oxide Semiconductor) transistors connected to input pads are widely used in Integrated Circuits (IC). Such an input structure typically receives the voltage applied to an IC pad and supplies a reduced voltage to the IC thereby ensuring that the gate-to-source and gate-to-drain voltages of the IC transistors do not exceed a maximum allowable limit.
Currently known input structures fail to provide adequate protection for the gate oxide when no power is supplied to the IC and yet the pads of the IC continue to receive power. The problem is further compounded when ICs manufactured using deep submicron (e.g. 0.25 &mgr;m) CMOS technologies—where the gate-to-source and gate-to-drain voltages of an MOS transistor must remain below 3.5 volts—are used in a system requiring 5.5 volts to operate. When used in such a system, the IC must be able to withstand the application of 5.5 volts to its pads both when the power supply to the IC is on and when it is off.
FIG. 1
shows a known input structure
10
. Input structure
10
receives voltage Vin on pad
12
and supplies voltage Vout at the output terminal of inverter
22
. Input structure
10
suffers from contention, as described below. To force the voltage Vout to a low level when no voltage is applied to pad
12
, a user may place an external resistor (not shown) across pad
12
and the system ground. When such a resistor is used and a hiqh voltage is applied to pad
12
before tri-stating pad
12
, PMOS transistor
18
turns on, pulling node N
1
to a high voltage. At the same time, the external resistor pulls node N
1
to ground. Therefore, a contention develops between PMOS transistor
18
and the external transistor. If the pull-up capability of transistor
18
is greater than the pull-down capability of the external resistor, voltage Vout remains at the high level.
FIG. 2
shows known input structure
30
. Input structure
30
does not have the contention problem of input structure
10
but consumes too much DC power because PMOS transistor
36
is never completely turned off.
FIG. 3
shows known input structure
50
. Input structure
50
does not have the contention problem of input structure
10
nor does it have the excessive power consumption of input structure
30
but it suffers from a major disadvantage. To avoid the natural hysterisis in input structure
50
, PMOS transistors
56
and
58
must be made large to meet the required threshold high and low specifications and which, in turn, makes the input structure undesirably slow.
In yet other known input structures (not shown) the MOS transistors are formed using thick gate oxides to protect against the pad over-voltage when the supply voltage is tuned off. Therefore, an IC containing such an input structure requires a manufacturing process that supports both regular and thick gate oxide MOS transistors and is thus expensive.
Therefor, a need exists for an input structure for protecting the internal circuitry of an IC when the pads of the IC continue to receive power but the supply power to the IC is turned off, and which overcomes the known problems of the existing input structures discussed above.
SUMMARY OF THE INVENTION
An input structure for an Integrated Circuit (IC), in accordance with one embodiment of the present invention, includes a first group of transistors for dividing the IC pad voltage, a second group of transistors for transferring the IC supply voltage, and a transistor for coupling the first and the second groups of transistors.
The input structure further includes a buffer circuit which receives either the divided pad voltage or the transferred supply voltage and generates a voltage that is applied to the IC.
When the supply voltage to the IC is turned off, the first group of transistors divides the pad voltage and supplies it to the buffer circuit. During this time, the coupling transistor remains conducting to disable the second group of transistors. When the supply voltage to the IC is turned on, some of the transistors in the first group and the coupling transistor are turned off. Transistors in the second group transfer the supply voltage to the buffer circuit.
The buffer circuit includes a first inverter coupled to additional transistors to ensure that the gate-to-source and gate-to-drain voltage of the inverter transistors do not exceed a specified limit. A second inverter of the buffer receives the output voltage of the first buffer and supplies the voltage to the IC.
REFERENCES:
patent: 5184031 (1993-02-01), Hayakawa et al.
patent: 5457421 (1995-10-01), Tanabe
patent: 5812017 (1998-09-01), Golla et al.
patent: 5886561 (1999-03-01), Eitan et al.
patent: 5914626 (1999-06-01), Kim et al.
Dinh Paul
Kwok Edward C.
National Semiconductor Corporation
Skjerven Morrill & MacPherson
Wells Kenneth B.
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