Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-06-02
2001-11-13
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S257000, C330S261000
Reexamination Certificate
active
06316995
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to amplifier circuits and, in particular, to a constant gm amplifier circuits capable of operating near the power supply rails.
2. Description of Related Art
Referring to the drawings,
FIG. 1
is a block diagram of a conventional constant gm amplifier A and associated circuitry configured to provide a regulated current output IA. In the disclosed embodiment, the output current is used to charge a capacitor C. The amplifier has a differential input with a built in input offset voltage. The inverting and non-inverting inputs of amplifier A are connected across a resistor RA. The output of the amplifier drives a PNP transistor Qx, the collector of which is coupled to resistor RA by way of a diode D
1
. The emitter of Qx is connected to a positive supply voltage VCC by way of a bias circuit BC. In the disclosed example, the supply voltage VCC may fall in the range of +3 to +30 volts.
Amplifier A operates to maintain a voltage across resistor RA at a value equal to the input offset voltage of the amplifier. That offset voltage is typically set to be on the order of tens of millivolts. If the voltage across RA is too large, the output of amplifier A will increase thereby decreasing the base-emitter voltage of Qx. This will reduce the current flow through IA through resistor RA. Similarly, a drop in voltage across RA will cause the base-emitter voltage to increase so that the current IA will increase. Thus, current IA is a regulated current. The current is used to charge a capacitor so as to produce a linearly changing voltage across capacitor C.
Since the voltage across capacitor C can drop to essentially zero volt and can increase to a value approaching VCC, Amplifier A must be implemented to function even when the inputs to the amplifier are close to the upper and lower power supply rails.
FIG. 2
is a simplified schematic diagram of part of a conventional input stage for amplifier A. Two differential transistor pair are used in order to provide the at or near rail-to-rail operation. A first transistor pair, NPN transistors QA and QB, have respective bases that receive differential input In+ and In−. When the common mode voltage, the average value of In+ and In−, approaches the positive supply rail, transistors QA and QB are active and provide at their collectors a differential output current which is further amplifier by an intermediate stage (not depicted) following the input stage. When the common mode input voltage approaches the negative supply rail, ground in this case, a second pair of transistors, PNP transistors QC and QD, are active. The differential input In+ and In− is applied to the respective based of transistors QC and QD. Again, the differential output current at the collectors of QC and QD is further amplified by the following stage.
An emitter resistor RB is connected between the emitter of transistor QD and the tail current source IB so as to introduce an input offset voltage when pair QC and QD are active. A second emitter resistor RC, equal in value to RB, is connected between the emitter of transistor QA and the output of the current mirror circuit transistor QG. Resistor RC operates to introduce an input offset voltage when transistor pair QA and QB are active. The offset voltages produced by resistor RB and RC are ideally equal in value. In a typical implementation, resistors RB and RC are both 2 k ohms.
A current source IB is connected as a tail current source for differential pair QC and QD. IB has a typical value of 10 microamperes. A pair of NPN transistors QF and QG are connected as a current mirror and function as the tail current source for differential pair QA and QB. A PNP transistor QE has a collector connected to the collector-base short of QF, the input of the current mirror, an emitter connected to the output of tail current source IB and a base connected to a bias voltage source VB.
The positive component In+ is roughly indicative of the common mode input voltage, the average value of In+ and In−. When In+ is less than the value of bias voltage VB, the emitter voltage of transistor QE is sufficiently low relative to the base voltage to cause transistor QE to be off. Thus, the input to the current mirror circuit will be zero as will the output at the collector of QG. Accordingly, transistor pair QA/QB, which operates using the current mirror output as the tail current source, will be inactive. Transistor pair QC and QD will be active, with these transistor being capable of operation with inputs essentially at the negative supply rail (ground potential).
Assuming that value of In+ exceeds the value of VB, transistor QE will become conductive. All of the current from source IB will flow through transistors QE rather than QC and QD so that pair QC/QD become inactive. The current flow IB through QE will mirrored by the current mirror circuit so that the collector current of QG will be equal to IB. Thus, transistors QA and QB will become active, with these transistors being capable of operation at or near the positive supply rail.
The input offset voltage when pair QC/QD is active due to the presence of resistor RB and is equal to RB(IB/2) or 10 millivolts in the present example.
Similarly, the input offset voltage when pair QA/QB is active is equal in lieu thereof RC(ICE/2), with ICE being the collector current of transistor QG. Assuming that RB and RC are equal and that IB and ICE are equal, the offset voltage is the same, 10 millivolts, independent of which transistor pair is active.
As previously noted, the voltage drop across resistor RA (
FIG. 1
) is maintained equal to the input offset voltage of amplifier A. Thus, a regulated current IA is produced which, in the present example, is used to charge capacitor C. Although the voltage drop across resistor RA, the difference between the voltages at In+ and In−, is regulated to be 10 millivolts, the average of the two voltages, the common mode voltage, will change as the charge on capacitor C changes. Depending upon the value of the voltage at the junction of resistor RA and diode D
1
, either transistor pair QA/QB or pair QC/QD is active. Referring to
FIG. 3
, the depicted graph shows the relationship between the regulated output current IA of the circuit of
FIG. 1
, using the conventional input stage of
FIG. 2
, and the voltage In+ applied to the non-inverting input of the amplifier A. Voltage VB of the
FIG. 2
circuit is set at about +4.4 volts. Depending upon the actual positive and negative supply rail voltages, it is preferable that voltage VB be selected so as to be significantly closer to one or the other supply rails so that only one of the transistor pair is active for most of the operating conditions. This is preferable to setting VB at some midpoint which would increase the likelihood the circuit will be frequently switching between the two pair.
When In+ is substantially less than VB, it can be seen by inspection of the circuit of
FIG. 2
that the regulated current IA is determined by the voltage drop across resistor RB, the voltage that creates the input offset voltage dropped across resistor RA. That voltage is nominally IB/2(RB) or 10 millivolts. When In+ is substantially greater than VB, the input offset voltage is determined by the voltage drop across RC. Again, that voltage is nominally IB/2(RC). However, when the input Vin+ is close to VB, the graph of
FIG. 3
shows that the input offset voltage drops substantially thereby causing the current flow through resistor RA to drop from a nominal value of 40 milliamperes to approximately only 15 milliamperes.
The drop in input offset voltage is due to the fact that the current flow IB/2 through resistor RB does not instantly switch to resistor RC, particularly when In+ or the common mode input voltage is constant or changing slowly. Further, under these conditions where the common mode input voltage happens to fall near the tr
Chen Sean S.
Shacter Stuart B.
Girard & Equitz LLP
National Semiconductor Corporation
Shingleton Michael B
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