Input stage for CMOS operational amplifier and method thereof

Details Input stage for CMOS operational amplifier and method thereof Input stage for CMOS operational amplifier and method thereof

1994-11-02

1996-03-19

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including differential amplifier

330258, 330261, H03F 345

Patent

active

055006248

ABSTRACT:
A CMOS amplifier input stage (10) has an n-channel differential input transistor pair (12, 14) and a p-channel differential input pair (26, 28) for receiving an input signal (V.sub.p, V.sub.m). Each transistor pair is respectively coupled to current shunt transistors (20, 32) and to current source transistors (16, 30) that generate currents that are inversely proportional to transistor mobilities. Bias generators (24, 34) apply a voltage to the gates of the shunting transistors respectively. When the input stage receives a common mode signal equal to the voltage applied by the bias generators, three-fourths of transistor (16) current flows through shunt transistor (20). Likewise, three-fourths of transistor (30) current flows through shunt transistor (32). As a result, the transconductance of the n-channel differential input transistor pair is matched to the transconductance of the p-channel differential input pair, and the transconductance of the input stage remains constant throughout the common mode range for the input stage of the amplifier.

REFERENCES:
patent: 4555673 (1985-11-01), Huijsing et al.
patent: 4890052 (1989-12-01), Hellums
patent: 5311145 (1994-05-01), Huijsing
patent: 5381112 (1995-01-01), Rybicki et al.
W. S. Wu et al., "Digital-Compatible High-Performance Operational Amplifier with Rail-to-Rail Input and Output Ranges," IEEE Journal, vol. 29, No. 1, Jan. 1994, pp. 63-66.
A. Coban et al., "A 1.75V Rail-to-Rail CMOS Op Amp," IEEE Int. Symposium on Circuits and Systems, vol. 5, 1994 pp. 497-500.

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