Input signal reading circuit having a small delay and a high fid

Details Input signal reading circuit having a small delay and a high fid Input signal reading circuit having a small delay and a high fid

1997-11-10

1999-12-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By pulse width or spacing

327 18, H03K 908

Patent

active

060086726

ABSTRACT:
An input signal reading circuit includes an up-down counter receiving an input signal and a sampling clock to count up the samplig clock when the input signal is at a high level and to count down the sampling clock when the input signal is at a low level. The up-down counter outputs an underflow signal when a count value of the up-down counter becomes zero. A comparator compares the count value of the up-down counter with a reference value held in a register, to generate a coincidence signal when the count value of the up-down counter becomes coincident with the reference value. A RS flipflop is set by the coincidence signal to bring the read-out signal into a high level, and is reset by the underflow signal to bring the read-out signal into a low level.

REFERENCES:
patent: 3629710 (1971-12-01), Durland
patent: 3836858 (1974-09-01), Kitano
patent: 4375084 (1983-02-01), Urushibata
patent: 4502024 (1985-02-01), Nishikawa
patent: 4502117 (1985-02-01), Kihara
patent: 4667338 (1987-05-01), Toyonaga et al.
patent: 4805199 (1989-02-01), Muramatsu
patent: 5043653 (1991-08-01), Foster et al.

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