Input register for test operand generation

Details Input register for test operand generation Input register for test operand generation

1987-10-23

1989-07-11

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 102

Patent

active

048478008

ABSTRACT:
Sequential faults are not tested for adequately when using test input operands generated in the chip from a random number generator to test the logic circuits in a very large scale integrated (VLSI) chip. Accordingly this application teaches the efficient construction of a test operand generator, using an input register with properly randomized feedback to break up sequential patterns which would otherwise develop in the input register.

REFERENCES:
patent: 3780275 (1973-12-01), Nakamura
patent: 3881099 (1975-04-01), Ailett et al.
patent: 3911216 (1975-10-01), Bartek et al.
patent: 4142239 (1979-02-01), Proto
patent: 4748576 (1988-05-01), Beker et al.

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