Input protection circuit for semiconductor integrated circuit de

Details Input protection circuit for semiconductor integrated circuit de Input protection circuit for semiconductor integrated circuit de

1989-10-24

1991-02-19

James, Andrew J.

357 13, 357 20, 357 35, 357 46, 357 49, H01L 2906, H01L 2972, H01L 2702

Patent

active

049948741

ABSTRACT:
First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad. The first impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the first and third impurity regions constitute a first bipolar transistor for input protection and the second impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the second and third impurity regions constitute a second bipolar transistor for input protection. The resistor and the first and second bipolar transistors constitute an input protection circuit.

REFERENCES:
patent: 4733285 (1988-03-01), Ishioka et al.
patent: 4789917 (1988-12-01), Miller
patent: 4819047 (1989-04-01), Gilfeather et al.
patent: 4849654 (1989-07-01), Okado

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