Input protection circuit for MOS device

Details Input protection circuit for MOS device Input protection circuit for MOS device

1989-07-13

1990-10-09

Jennings, Derek S.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361111, 357 2313, H02H 320

Patent

active

049623206

ABSTRACT:
An input protection circuit for MOS devices includes a first resistor and a first parasitic bipolar transistor connected between an input pad and an input buffer circuit of a MOS device. The input protection circuit for MOS devices further includes a second resistor and a second parasitic bipolar transistor connected at a preceding stage of the input buffer circuit so that the gate oxide film of the input buffer circuit can be protected from being damaged by static charges or a voltage which is accidentally generated, without increasing the pattern size of the first parasitic bipolar transistor.

REFERENCES:
patent: 4586104 (1986-04-01), Standler
patent: 4663584 (1987-05-01), Okada et al.
patent: 4740715 (1988-04-01), Okada
patent: 4745450 (1988-05-01), Hartranft et al.
patent: 4807080 (1989-02-01), Clark
patent: 4819047 (1989-04-01), Gilfeather et al.
patent: 4849654 (1989-07-01), Okada

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