Input protection circuit for CMOS devices

Details Input protection circuit for CMOS devices Input protection circuit for CMOS devices

1990-01-17

1992-10-27

DeBoer, Todd E.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361 58, 357 2313, H02H 904

Patent

active

051595184

ABSTRACT:
An input protection circuit protects MOS semiconductor circuits from electrostatic discharge voltages and from developing circuit latchup. The input protection circuit includes a low resistance input resistor, and two complementary true gated diodes. One true gated diode has a P-doped node coupled to the input node, and a gate and N-doped node coupled to a high voltage power supply node. The other true gated diode has a N-doped node coupled to the input node, and a gate and P-doped node coupled to a second power supply node.

REFERENCES:
patent: 4930037 (1990-05-01), Woo

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