Input protection circuit and output driver circuit comprising MI

Details Input protection circuit and output driver circuit comprising MI Input protection circuit and output driver circuit comprising MI

1989-10-17

1992-02-04

Hille, Rolf

357 238, 357 2312, 357 59, H01L 2910, H01L 2978, H01L 2968, H01L 2904

Patent

active

050863223

ABSTRACT:
An MIS transistor comprises first and second concave grooves (17, 17) opposing to each other with a gate electrode (4, 39) provided therebetween. Source and drain regions (8a, 8b, 31, 34) are formed on sidewalls of the concave grooves. A configuration of the sidewall surface of the concave groove is selected such that a current density of a punch through current between the source and drain regions becomes uniform. Furthermore, a concave groove having such a configuration, for example, a taper configuration in which a space between sidwwall surfaces becomes narrower toward a bottom portion of the substrate, is formed by the reactive ion etching.
The MIS transistor is employed in an input protection circuit or an output driver circuit, which enables high integration of the device and improves an input breakdown voltage.

REFERENCES:
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4153906 (1979-05-01), Shinoda et al.
patent: 4285116 (1981-08-01), Meguro
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4378506 (1983-03-01), Taira
Hsu et al., "Multiple V-Groove FET", IBM Technical Disclosure Bulletin, vol. 19, No. 6 (Nov. 1976), pp. 2135-2136.
Anantha et al., "Self-Aligned IGFET with Silicon Dioxide Isolated Source and Drain", IBM Technical Disclosure Bulletin, vol. 22, No. 11 (Apr. 1980), pp. 4895-4899.
OH et al., "A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes", IEEE Electron Device Letters, vol. EDL-5, No. 10 (Oct. 1984), pp. 400-402.

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