Input protection arrangement for VLSI integrated circuit devices

Details Input protection arrangement for VLSI integrated circuit devices Input protection arrangement for VLSI integrated circuit devices

1989-11-16

1990-08-28

James, Andrew J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

357 238, 361 56, H01L 2978

Patent

active

049529943

ABSTRACT:
An input protection arrangement for diverting current from high voltages due to, for example electrostatic discharges into a bonding pad of an integrated circuit chip. The chip has a bonding pad connected to a conducting path and to a source or drain region of an insulated gate field effect transistor, the other region being connected to a power bus on the chip. The conducting path runs between the source and drain regions and operates as the gate terminal of the transistor. The conducting path is insulated from the surface of the chip by a field oxide insulating layer of a substantially uniform thickness to prevent rupture of the oxide between the gate and the source and drain regions in the event of high-voltages. The source and drain regions include regions of conventional doping levels having depths corresponding to the depths of the other corresponding regions on the chip, surrounded by large wells of lower doping levels. The input pad is separated from the chip substrate by an insulating oxide layer and by a doped well of the same conductivity type as the source and drain regions of the transistor to reduce the input capacitance and prevent punch through from the pad to the substrate.

REFERENCES:
patent: 3395290 (1963-07-01), Farina et al.
patent: 3400310 (1968-09-01), Dorendorf
patent: 4400711 (1983-08-01), Avery
patent: 4730208 (1988-03-01), Sugino
Patent Abstracts of Japan, vol. 9, No. 189 (E-333)[1912], 6th Aug. 1985; & JP-A-60058652 (Nippon Denki K.K.) 04-04-198.
JP-A-60058652 (Nippon Denki K.K.) 04-04-1985.

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