Input panel avoiding interference pattern and method of forming

Telegraphy – Systems – Position coordinate determination for writing

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Details

178 19, 345173, 345174, 345175, G08C 2100, G09G 302

Patent

active

056683537

ABSTRACT:
An input panel of a resistance layer type includes a first board having a first transparent conductive layer on its surface and a second board having a second transparent conductive layer on its surface. The first board and the second board are arranged such that the first transparent conductive layer faces the second transparent conductive layer. The input panel further includes first spacers arranged between the first board and the second board, the first spacers being non-conductive and having a height no greater than 14 .mu.m, and second spacers arranged between the first board and the second board among the first spacers, the second spacers being non-conductive and having a height no smaller than 15 .mu.m.

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patent: 4700025 (1987-10-01), Hatayama
patent: 4818827 (1989-04-01), Ipcinski
patent: 5010213 (1991-04-01), Moriwaki
patent: 5172101 (1992-12-01), Bates
patent: 5220136 (1993-06-01), Kent
patent: 5262778 (1993-11-01), Saunders

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