Input-output unit having extended addressing capability

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G06F 910

Patent

active

040927156

ABSTRACT:
In a data processing system employing paging and segmentation for storing information in memory, the input-output unit is provided with addressing capability for addressing and accessing memory without the intervention of the central processing unit. Page tables are set up in memory containing page table words, and a page table is assigned to each peripheral. A peripheral control word assigned to each peripheral includes a pointer to the start of the peripheral's page table whereby the peripheral through the I/O unit can locate its assigned page table, and page table words therein are combined with other control words to access paged memory locations.
In one mode of operation an extended addressing mechanism is provided which allows the generation of absolute addresses of paged memory locations having an address field larger than the address field of the control words used to access such paged memory locations.

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patent: 3938096 (1976-02-01), Brown et al.
patent: 3947823 (1976-03-01), Padegs et al.
patent: 3955180 (1976-05-01), Hirtle
patent: 3970999 (1976-07-01), Elward
patent: 3976978 (1976-08-01), Patterson et al.

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