Input/output system for a massively parallel, single instruction

Details Input/output system for a massively parallel, single instruction Input/output system for a massively parallel, single instruction

1993-11-22

1995-04-25

Bowler, Alyssa H.

Boots, shoes, and leggings

395250, 395275, 395425, 364DIG1, 3642319, G06F 506, G06F 1312, G06F 1516, G06F 700

Patent

active

054107270

ABSTRACT:
A two-dimensional input/output system for a massively parallel SIMD computer system providing an interface for the two-way transfer of data between a host computer and the SIMD computer. A plurality of buffers equal in number, and distributed with the individual processing elements of the SIMD computer are used to provide a temporary storage area which allows data in different formats to be mapped in a format suitable for transfer to the host computer or for transfer to the SIMD processing elements. The temporary storage is controlled in such a way as to transfer entire blocks of data in a single SIMD system clock cycle thereby achieving an input/output data rate of N bits/cycle for a SIMD computer consisting of N processors. The system is capable of handling irregular as well as regular data structures. The system also emphasizes a distributed approach in having the input/output system divided into N pieces and distributed to each processor to reduce the wiring complexity while maintaining the I/O rate.

REFERENCES:
patent: 3287703 (1966-11-01), Slotnick
patent: 3936806 (1976-02-01), Batcher
patent: 3979728 (1976-09-01), Reddauay
patent: 4065808 (1977-12-01), Schomberg et al.
patent: 4101960 (1978-07-01), Stokes et al.
patent: 4380046 (1983-04-01), Prosch et al.
patent: 4380046 (1983-04-01), Forsl et al.
patent: 4481580 (1984-11-01), Martin et al.
patent: 4484262 (1984-11-01), Sullivan et al.
patent: 4514807 (1985-04-01), Nogi
patent: 4523273 (1985-06-01), Adams, III et al.
patent: 4546433 (1985-10-01), Tucker
patent: 4601055 (1986-07-01), Kent
patent: 4665556 (1987-05-01), Fukushima et al.
patent: 4707781 (1987-11-01), Sullivan et al.
patent: 4709327 (1987-11-01), Hillis et al.
patent: 4727474 (1988-02-01), Batcher
patent: 4773038 (1988-09-01), Hillis et al.
patent: 4783738 (1988-11-01), Li et al.
patent: 4901224 (1990-02-01), Ewert
patent: 4972314 (1990-11-01), Getzinger et al.
patent: 5081575 (1992-01-01), Hiller et al.
patent: 5136717 (1992-08-01), Morley et al.
patent: 5148547 (1992-09-01), Kahle et al.
D. Parkinson et al., "The AMT DAP 500," Compcon 88-Thirty IEEE Computer Society International Conference, San Francisco, Calif., Spring 1988, IEEE, New York, pp. 196-199.
Wiackless; Massively parallel computer for Digital Signal and Image Processing; May 1989 IEEE.
Roberts; Recent developments in parallel processing; IEEE.

Affiliated with

Also associated with

Rating

Input/output system for a massively parallel, single instruction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input/output system for a massively parallel, single instruction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input/output system for a massively parallel, single instruction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1574847