Patent
1995-12-29
1999-01-05
Chan, Eddie P.
395739, 395281, G06F 1324
Patent
active
058570900
ABSTRACT:
A computer system is described having one or more host processors, a host chipset and a input/output (I/O) subsystem. The host processors are connected to the host chipset by a host bus. The host chipset is connected to the input/output subsystem by a primary personal computer interface (PCI) bus. The I/O subsystem is connected to I/O devices by a secondary PCI bus. The I/O subsystem includes advanced programmable interrupt controller (APIC) functionality typically provided within an I/O APIC chip within a host chipset. The APIC functionality of the I/O subsystem is primarily implemented in software executing on a core processor of the I/O subsystem. The software creates and accesses various APIC registers and tables, such as a redirection table, within a memory of the I/O subsystem. A single 3-wire APIC bus interconnects the host processors with the I/O subsystem. With this arrangement, non-PCI interrupt lines from the I/O devices are connected only into the I/O subsystem, rather than into the host chipset.
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Davis Barry R.
Young Bruce
Chan Eddie P.
Intel Corporation
Portka Gary J.
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