Input/Output regulating circuitry with...

Details Input/Output regulating circuitry with... Input/Output regulating circuitry with...

2008-02-27

2010-11-30

Vu, Bao Q. (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S054000, C361S056000, C361S091500

Reexamination Certificate

active

07843672

ABSTRACT:
An I/O regulating circuitry is provided. The I/O regulating circuitry omits the ESD device in a CMOS process with a minimized critical dimension to reduce chip size while still maintaining electrostatic discharge immunity. The I/O regulating circuitry is applied in MLC flash memory applications and the flash controller thereof.

REFERENCES:
patent: 6282145 (2001-08-01), Tran et al.
patent: 6751118 (2004-06-01), Tran et al.
patent: 6956779 (2005-10-01), Tran

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