Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
1999-09-22
2002-07-02
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
C361S111000, C361S056000, C361S058000
Reexamination Certificate
active
06414341
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input/output (I/O) protective device that protects an internal circuit in a semiconductor device from external noise such as a surge and the static electricity, and more particularly to an input/output protective device capable to provide a protection even against high voltage external noise having rapid rising characteristics.
2. Description of the Related Art
A semiconductor device, in general, comprises an internal circuit to realize a prescribed function, a pad that is connected to this internal circuit and used for input and output of signals and a lead terminal being connected to this pad. This lead terminal is then connected with an electric circuit outside, when required. An input/output protective device for a semiconductor device is set between the internal circuit and the pad for input/output, and if external noise such as a surge and the static electricity is applied to the lead terminal, the input/output protective device prevents such external noise to degrade the internal circuit therein by inducing an electric discharge in a protective element that comprises a transistor, a diode or the like.
For instance, in JP-A-3-248567, there is disclosed a structure in which aluminum wiring
31
of a drain node and a source node are, respectively, connected to a conductive layer
36
through contacts
33
and this conductive layer
36
is connected to a diffusion layer
34
through a contact
35
having an elongated contact hole, as shown in FIG.
8
. When external noise such as a surge is applied thereto, this structure prevents the electric field centralization on a certain region of the diffusion layer
34
from developing and, thus, a contact therein from being degraded.
Further, JP-B-8-24183 discloses that, in a semiconductor device that has, as shown in
FIG. 9
, a first diffusion region
46
and a second diffusion region
48
, both of which are substantially rectangular in shape and formed in an element region isolated by a field oxide film
42
, sandwiching a gate electrode
42
, and contact apertures
41
and
47
disposed in these first and second diffusion regions, the electric field centralization is liable to develop on a boundary point
43
in a corner section of the first diffusion region
46
on the gate electrode side, which easily leads to the generation of the electrostatic stress. For the purpose of overcoming this problem, the invention in said publication discloses a structure, wherein recess sections
45
are set in each corner section of the first diffusion region
46
on the opposite side to the gate electrode
44
and formed in such a way that the ratio of the length L of the side of said recess section which is substantially parallel to the boundary line between the first diffusion region
46
and the gate electrode
44
to the distance d from this side to the gate electrode is 1.5 or more. In this instance, setting recess sections
45
in the first diffusion region
46
lengthens the path from a contact aperture
41
to the boundary point
43
and increases the diffusion resistance, and thereby the electric field centralization on the boundary point can be made to relax.
With respect to such an input/output protective device, the protective ability thereof has been, hitherto, evaluated by the machine model method (referred to as the MM method, hereinafter), the human body method (referred to as the HBM method, hereinafter) or the like. The standard of the actual test method for the MM method is being defined by the Electronic Industries Association of Japan (referred to as EIAJ, hereinafter) and, in the U.S., by the EOS/ESD Association. The MM method in conformity with the EIAJ is referred to as the EIAJ method, and the MM method in conformity with the EOS/ESD Association, as the EOS/ESD method, hereinafter.
FIG.
6
(
a
) illustrates the set-up of a test device. In the test method for the MM method, a capacitor C
0
with a capacitance of 200 pF is charged to a prescribed test voltage and electrostatic discharge is applied to a lead terminal (not shown in the drawing) connected with a pad
53
of a semiconductor device
100
, and then the evaluation of the voltage level to cause the breakdown of the semiconductor device is made. In practice, a test operator first applies a voltage of 50 V to a capacitor C
0
as a test voltage and then turns on a switch SW, actuating the electrostatic discharge which is applied to a protective element
101
through a lead terminal and a pad
53
in each semiconductor device
100
. After that, using a tester (not shown in the drawing), the test operator carries out the function test for the semiconductor devices
100
to find out whether each semiconductor device
100
can operate normally or not, and counts the number of degraded semiconductor devices
100
. Subsequently, the test operator performs similar tests at a number of test voltages increased every 50 V and repeats Lt counting the number of degraded semiconductor devices
100
each time.
FIG.
6
(
a
) shows a simulation model of the test according to the MM method for obtaining the waveform of a current flowing through the protective element
101
in the semiconductor device
100
by means of calculation, while FIG.
6
(
b
) shows a plan view of the semiconductor device
100
. The simulation model shown in FIG.
6
(
a
) is composed of a test device
200
and the semiconductor device
100
to be tested. The test device
200
consists of a capacitor C
0
with a capacitance of 200 pF that is to be charged to a test voltage and a parasitic inductor L, a parasitic resistor R and a parasitic capacitor C of the test device
200
as well as a switch SW to apply the test voltage to the semiconductor device
100
.
The semiconductor device comprises a protective element formed on a P-type substrate
51
, a pad
53
connected thereto and a lead terminal (not shown in the drawing) connected thereto. The protective element
101
has two N
+
-diffusion layers
52
a
and
52
b
and these N
+
-diffusion layers
52
a
and
52
b
are disposed at a given space, facing each other. Between the N
+
-diffusion layers
52
a
and
52
b
, the P-type substrate
51
is present so that the protective element
101
shown in
FIG. 6
forms an NPN parasitic transistor. An insulating film
54
is formed over the N
+
-diffusion layers
52
a
and
52
b
, and metal wirings
55
a
and
55
b
are formed thereon. The metal wirings
55
a
and
55
b
are connected through contacts
56
a
-
56
e
and
57
a
-
57
e
to the N
30
-diffusion layers
52
a
and
52
b
, respectively. Further, the N
+
-diffusion layer
52
a
is connected through the metal wiring
55
a
and the pad
53
to the lead terminal (not shown in the drawing), while the N
+
-diffusion layer
52
b
is connected through the metal wiring
55
b
and a contact
58
to the P-type substrate
51
and consequently to the ground.
Using the device simulator for the semiconductor device
100
, the present inventors conducted simulation with the equivalent circuit shown in
FIG. 6
to find out what effects these evaluation test methods, EIAJ method and EOS/ESD method, have on the actual protective element
101
, respectively.
In the test device
200
shown in FIG.
6
(
a
), for the EIAJ method, the parasitic capacitor C had a capacitance of 20 pF, the parasitic inductor L, an inductance of 10 &mgr;H and the parasitic resistor R, a resistance of 10&OHgr;, while, for the EOS/ESD method, the parasitic capacitor C had a capacitance of 7 pF, the parasitic inductor L, an inductance of 0.5 &mgr;H and the parasitic resistor R, a resistance of 10&OHgr;. Further, in the calculation, the test voltage to charge the capacitor C
0
with a capacitance of 200 pF was taken to be 50 V.
FIGS.
7
(
a
) and (
b
) show the results of the simulation when the test voltage was applied, for the EIAJ method and the EOS/ESD method, respectively. In these graphs, the value of the current flowing the test device
200
to the protective element
101
in the s
Chaudhuri Olik
Ha Nathan W.
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