Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-12-26
2004-01-20
Huynh, Kim (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000, C257S360000
Reexamination Certificate
active
06680833
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an input-output protection device, and in particular, to an input-output protection device for protecting a circuit from electrostatic discharge (ESD).
Referring to FIG.
1
and
FIG. 2
, description will be made about a circuit of a most general nMOS protection device as the conventional input-output protection device.
In this example, when an ESD-voltage is stressed to an input-output pad
5
, a nMOS protection device
12
is turned on, and an ESD-current flows into a ground terminal
9
. In other words, the ESD-current is bypassed through the ground terminal
9
. Thereby, a circuit
10
a
is protected.
When a negative polarity ESD-voltage is stressed to the input-output pad
5
for the ground terminal
9
, a PN junction between an N-type drain diffusion layer
7
a
and a P-well
3
is put into a forward bias. Consequently, the ESD-current is bypassed through a forward PN diode.
Further, a sufficient ESD robustness is kept because a clamp voltage due to a forward diode is low, generally, 1V or less.
When a positive polarity ESD-voltage is stressed to the input-output pad
5
for the ground terminal
9
, the PN junction between the N-type drain diffusion layer
7
a
and the P-well
3
is put into a reverse bias.
When a high reverse voltage is given to the PN junction, an avalanche breakdown phenomenon occurs in the PN junction. Thereby, a breakdown current flows from the N-type drain diffusion layer
7
a
into the P-type diffusion layer
8
.
Because of the breakdown current the voltage-drop occurs at the P-well
3
. As a result, the forward bias appears between the P-well
3
and the N-type source diffusion layer
7
b.
Further, a parasitic NPN bipolar transistor, in which the N-type drain diffusion layer
7
a,
the P-well
3
, and the N-type source diffusion layer
7
b
serve as a collector, a base, and an emitter, respectively, is turned on.
Herein, a voltage-current characteristic in this state is illustrated in FIG.
3
.
The breakdown phenomenon takes place at a voltage value Vbd. When the breakdown current reaches a current value It
1
, the parasitic NPN bipolar transistor is turned on, and the current flows on the condition that the voltage is held to Vsp.
Such a phenomenon is generally called a snapback. Further, Vt
1
is referred to as a snapback trigger voltage while Vsp is referred to as a snapback holding voltage.
In a recent semiconductor integrated circuit, the device has been rapidly reduced in size because of high-density and high-speed.
Under this circumstance, ESD robustness is remarkably degraded because of thinner gate oxide, shallower drain junction and silicided diffusion.
In consequence, ESD protection device of high ESD robustness becomes more difficult.
To solve such a problem, it is necessary to lower the snapback trigger voltage. Several suggestions have been made about methods for raising up the gate potential of the nMOS protection device only when the ESD-current flows as the solving measures.
Referring to FIG.
4
through
FIG. 6
, description will be made about examples of circuits for solving the above-mentioned problems.
The circuit illustrated in
FIG. 4
has been suggested by Sridhar Ramaswamy et. al., “EOS/ESD Reliability of Deep Sub-Micron NMOS Protection Devices,” IEEE Transactions 1995, pages 284-291.
In this example, the input-output pad
5
and the gate of the nMOS protection device
12
are coupled via a capacitor device
18
, and a resistor device
17
is connected between the gate of the nMOS protection device
12
and the ground terminal
9
.
With such a structure, when the positive polarity ESD-voltage is stressed to the input-output pad
5
for the ground terminal
9
, the gate voltage of the nMOS protection device
12
raises up transiently by a capacitor coupling effect.
A timing, at which the gate voltage raises up, is adjusted in dependence upon the values of the capacitor device
18
and the resistor device
17
, and is selected such that the nMOS protection device is put into an off state when the integrated circuit is normally operated.
When the gate voltage of the nMOS protection device raises up due to transient ESD-current, an impact-ionization effect becomes high at a drain edge portion. As a result, the current, which flows from the N-type drain into the P-well, is increased, and the snapback trigger voltage is reduced.
When the snapback trigger voltage is reduced, the nMOS protection device can turn on at a lower voltage. Thereby, the ESD robustness can be improved.
In an example illustrated in
FIG. 5
, the gate voltage of the nMOS protection device raises up by utilizing a zener diode
22
.
While, in an example illustrated in
FIG. 6
, the gate voltage rise up by the use of a PNP transistor
23
and a capacitor device
18
.
Herein, it is noted that the both examples have been disclosed in EOS/ESD Symposium Proceedings, 1997.
As mentioned above, it is applied the gate voltage rise up effect due to transient ESD-current in order to improve ESD robustness.
Although the gate voltage of the MOS transistor raises up when the ESD-voltage is given thereto as mentioned described, the MOS protection device is put into the off state during the normal operation. Consequently, a signal of an internal circuit can not be given to the gate of the MOS protection device.
Accordingly, although the conventional ESD protection circuit is applicable as an only input protection device, but an output transistor, which drives by connecting the internal circuit to the gate, can not be applied as the protection device.
In consequence, an output-driving transistor is required in addition to the protection device with respect to an output pin of the integrated circuit. This inevitably causes to enlarge an output buffer in size.
In particular, all of I/O buffers must be enlarged in size in the integrated circuit, such as, a gate array that exchanges an input buffer and an output buffer by changing only a wiring layout using the buffer having the same structure, As a result, a chip size can not be reduced.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an input-output protection device, which is improved of ESD robustness degradation due to thinner gate oxide, shallower drain junction and silicided diffusion of an integrated circuit.
It is another object of this invention to provide an input-output protection device, which is applicable as any one of an input buffer, an output buffer, and a input/output buffer of an integrated circuit.
According to this invention, an input-output protection device is formed on a semiconductor substrate.
A MOS protection device has a drain diffusion layer, a gate, a source diffusion layer, and a body, respectively.
An input-output pad is connected to the drain diffusion layer. The gate connected to an internal circuit or ground terminal (power supply terminal).
A control circuit is connected to the body. Ground terminal (Power supply terminal) is connected to the source diffusion layer.
With such a structure, the body is electrically isolated from the semiconductor substrate.
In this case, the control circuit is connected to the body via a diffusion layer.
For example, the semiconductor substrate has a first conductive type, and the body is structured by a first well having the first conductive type.
In this condition, the body is electrically isolated from the semiconductor substrate via a second well having a second conductive type. Herein, the second conductive type is opposite to the first conductive type and a second well is formed between the first well and the semiconductor substrate.
Further, the second well may be coupled to the ground terminal (power supply terminal).
In this event, the first conductive type may be a P-type while the second conductive type may be an N-type.
Alternatively, the semiconductor substrate has a first conductive type, and the body is structured by a well having a first conductive type.
With this structure, the body is electrically isolated from the semiconductor substrate via an insulator.
Huynh Kim
NEC Electronics Corporation
Sughrue & Mion, PLLC
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