Input/output processor control system with a plurality of stagin

Details Input/output processor control system with a plurality of stagin Input/output processor control system with a plurality of stagin

1989-02-21

1992-02-11

Lee, Thomas C.

Boots, shoes, and leggings

3642405, 3642412, 3642513, 3642514, 364247, 3642472, 3642383, 3642386, 3642397, 364DIG1, G06F 1336, G06F 1338, G06F 1340

Patent

active

050880250

ABSTRACT:
A control system for multiple channel data transfers between a main bus and a data bus is provided. A novel input/output processor control which permits multiple word transfers to occur in a single predetermined time slot while resolving buffer access conflicts and includes staging buffers coupled to the main bus and data buffers coupled to the data bus. A J-Bus is coupled between the staging buffers and the data buffers and is controlled by J-Bus transfer controller. A D-Bus transfer controller controls information transferred to an from the data bus and the data buffers. An M-Bus transfer controller controls information transferred to and from the staging buffers and the M-Bus. A controllable time slot generator in addition to generating the time slots for transferring information between the data buffers on the J-Bus also provides means for resolving conflicts between the J-Bus and the D-Bus and the M-Bus.

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