Input/output paging mechanism in a data processor

Details Input/output paging mechanism in a data processor Input/output paging mechanism in a data processor

1983-07-25

1987-03-31

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 1206

Patent

active

046547916

ABSTRACT:
In a data processor performing an input and output paging function, a main memory (MMU) and an input and output processor (IOP) connected to the MMU through a bus are provided. The MMU stores a list-service page table for mapping a logical space in which channel command entries are located, and a data service page table for mapping the data transfer areas specified by channel command entries, pointers for the respective page tables, and flags for the designation of a physical or logical address. The IOP reads the pointers from the MMU, refers to the respective page tables, determines whether the specified address is physical or logical, and translates it into an effective address.

REFERENCES:
patent: 4084227 (1978-04-01), Bennett et al.
patent: 4155119 (1979-05-01), De Ward et al.
patent: 4173783 (1979-11-01), Couleur et al.
patent: 4319323 (1982-03-01), Ermolovich et al.

Affiliated with

Also associated with

Rating

Input/output paging mechanism in a data processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Input/output paging mechanism in a data processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input/output paging mechanism in a data processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2217260